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Text: 20 54F/74F20 Dual 4-Input N A N D G ate Connection Diagrams Ordering Code: See Section 5 Pin Assignment for LCC and PCC Pin Assignment for DIP and SOiC Input Loading/Fan-Out: See S ection 3 fo r U.L. d e fin itio n s Pin Names 54R74F U.L. HIGH/LOW Description
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54F/74F20
54R74F
54F/74F
54F/74F
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Text: 139 54F/74F139 Connection Diagrams Dual 1-of-4 Decoder Description The 'F 139 is a high-speed, dual 1-of-4 d eco der/dem u ltip lexer. The device has tw o independent decoders, each accepting tw o inputs and providing four m utually exclusive active LOW outputs. Each d ecoder has an active
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54F/74F139
54R74F
54F/74F
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Text: 843 54F/74F843 Connection Diagram 9-Bit Transparent Latch o e rr D d U tt T W T f r d K i Interface latch is designed to eliminate the extra packages requiredncB w ^ k i s t i n g latches and provide extra data width for wider ad d re ss/d m £ busgs carrying parity.
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54F/74F843
AM29843.
54F/74F
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Text: 395 54F/74F395 Connection Diagrams T— r 4-Bit Cascadable Shift Register 3-State Outputs m r The ’F 3 £ > Y a £ B lt S h if t R egister w ith serial and parallel synchronous operating W q ^ p P h r y fo u r 3-state b u ffe r ou tp u ts. The s h iftin g and loading
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54F/74F395
54F/74F
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