54SX Search Results

actel fpga 54sx32

Abstract: 54SX32 54SX16 54SX08 066V 54SX RT54SX
Contextual Info: Application Note Power-Up and Power-Down Behavior of 54SX and 54SX Devices I n tro du ct i on One of the key benefits of Actel’s nonvolatile antifuse FPGA technology is the ability of the devices to be live at power-up. Since no configuration PROMs are required to

54sx08

Abstract: THERMAL Fuse m20 tf 115 c
Contextual Info: v 3 .0 54SX Family FPGAs Leading Edge Performance • 100%Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3VOperation with 5.0VInput Tolerance • 3.7 nsClock-to-Out Pi n-to-Pi n • Very Low Power Consumption • 0.1 ns Input Set-Up

Contextual Info: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew

CQFP 256 PIN actel

Contextual Info: Pr el i mi nar y v 1. 3 54SX Family FPGAs RadTolerant and HiRel Features • 100% Resource Utilization with 100% Pin Locking RadTolerant 54SX Family • Mixed Voltage Support—3.3V Operation with 5.0V Input Tolerance • Tested Total Ionizing Dose TID Survivability Level

ACTEL BGA329

Abstract: LRD12 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 LRD-12 A54SX16P PQFP
Contextual Info: -m e te f v 3 .0 - m 54SX Fami ly FPGAs Leadi ng Edge P e r f o r m a n c e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-toOut Pin-to-Pin • \fcry Low Power Consumption

Contextual Info: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby

actel fpga 54sx32

Abstract: 54SX32 54SX RT54SX antifuse fpga
Contextual Info: Application Note AC145 Power-Up and Power-Down Behavior of 54SX and 54SX Devices I n tro du ct i on One of the key benefits of Actel’s nonvolatile antifuse FPGA technology is the ability of the devices to be live at power-up. Since no configuration PROMs are required to

actel

Abstract: A54SX32 54SX A54SX16
Contextual Info: Errata v2.0 54SX Family FPGAs RadTolerant and HiRel Errata In Table 1 on page 8, the Maximum Input Tolerance for the 54SX16 and 54SX32 devices is incorrect. Here is how the table should appear. Table 1 • Supply Voltages Devices 54SX16 54SX32 54SX16

Contextual Info: P r e l i m i n a r y v 1 .3 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput Tolerance • Tested Total IonizingDose TID Survivability Level

Contextual Info: 54SX Family FPGAs RadTolerant and HiRel Features R a d T ole ran t 54SX Family • • • • • TestedTotal Ionizing Dose TID Survivability Level Devices Avail able from Tested Lots Radiation Performance to 100K Rads Up to 160 MHz On-Chip Performance

b23n20

Contextual Info: ^ c te -m v 2. 0 l 54SX Family FPGAs • • • • • 100%Resource Utilization with 100%Pin Locking 3.3VOperation with 5.0VInput Tolerance Very Low Power Consumption Deterministic, User-ControlIableTiming Unique, In-System Diagnostic and Debug capability with

RTSX32

Abstract: 54SX A54SX16 A54SX32 RT54SX RT54SX72S RTSX16
Contextual Info: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby

THERMAL Fuse m20 tf 115 c

Abstract: 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 circuit diagram of motherboard W2-081 ac 171
Contextual Info: v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es • 320 MHz Internal Performance • 66 MHz PCI • 3.7 ns Clock-to-Out Pin-to-Pin • CPLD and FPGA Integration • 0.1 ns Input Set-Up • Single Chip Solution • 0.25 ns Clock Skew

RTSX32

Abstract: TRANSISTOR ASY 28 54SX A54SX16 A54SX32 RT54SX Cqfp256
Contextual Info: Preliminary v1.5.2 54SX Family FPGAs RadTolerant and HiRel Fe a t ur es • Up to 225 User I/Os Rad To ler ant 54S X Fam i ly • Up to 1,080 Dedicated Flip-Flops • Tested Total Ionizing Dose TID Survivability Level E asy L ogi c In teg ra ti on • Radiation Performance to 100Krads (Si) (ICC Standby

Contextual Info: Preliminary v1.5 54SX Family FPGAs RadTolerant and HiRel Fe a t ur es • Up to 225 User I/Os Rad To ler ant 54S X Fam i ly • Up to 1,080 Dedicated Flip-Flops • Tested Total Ionizing Dose TID Survivability Level E asy L ogi c In teg ra ti on • Radiation Performance to 100Krads (Si) (ICC Standby

ACTEL

Abstract: A54SX32 errata
Contextual Info: Errata v2.0 54SX Family FPGAs Errata In Table 1 on page 8, the supply voltage is incorrect. Here is how the table should appear. 54SX16-P has three different entries because it is capable of both a 3.3V and a 5V drive. Table 1 • Supply Voltages VCCA VCCI

k16 a21

Abstract: 313-pin
Contextual Info: ^ c M J P relim inary • v 1 .1 54SX Family FPGAs Features • 3.3VOperation with 5.0VInput Tolerance Hi gh P e r f o r m ance • Low Power Consumption • 320 MHz Internal Performance • Deterministic, User-ControlIableTiming • 4.0 nsClock-to-Out Pi n-to-Pi n

THERMAL Fuse m20 tf 115 c

Abstract: 54SX16A actel fpga 54sx32 54SX32
Contextual Info: ^ c te l v 2 .0 54SX Family FPGAs L ea d in g Edge Pe rform an ce • 100% Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3V Operation with 5.0V Input Tolerance • 3.7 ns Clock-to-Out Pm-to-Pin • Very Low Power Consumption

Contextual Info: W ie te l Preüminary - m v1 . 2 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput

ird8

Abstract: LRD12 54SX32 ic tny 176 TNY 227 TNY 251
Contextual Info: ^ c te l P re lim in a ry v l.1 54SX Family FPGAs RadTolerant and HiRel F e a tu re s R a d T o le r a n t 5 4 S X F a m ily • • • • • Tested Total Ionizing Dose TID Survivability Level Devices Available from Tested Lots Radiation Performance to 100K Rads

Contextual Info: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby

Orbit Semiconductor

Abstract: CQFP 208 PIN
Contextual Info: Pr el imin a ry v1 .4 54SX Family FPGAs RadTolerant and HiRel F e at u re s H i g h D e n s i ty D e v i c e s R a d T o l e r a n t 5 4 S X F a m i ly • 16,000 and 32,000 Available Logic Gates • Tested Total Ionizing Dose TID Survivability Level • Up to 225 User I/Os

54SX32

Abstract: TRANSISTOR ASY 28 tIRD12 DSA0036603 CQFP 256 PIN actel CQ25 54SX16
Contextual Info: Preliminary v1.5 54SX Family FPGAs RadTolerant and HiRel Fe a t ur es • Up to 225 User I/Os Rad To ler ant 54S X Fam i ly • Up to 1,080 Dedicated Flip-Flops • Tested Total Ionizing Dose TID Survivability Level E asy L ogi c In teg ra ti on • Radiation Performance to 100Krads (Si) (ICC Standby

54SX72

Abstract: CERAMIC PIN GRID ARRAY 144 pins blown fuse A2-A20 A54SX16A
Contextual Info: A d van ced v.1 54SXA Family FPGAs Specifications Output Tristate at Powerup • 8,000 to 72,000 Available Logic Gates • 100% Resource Utilization with 100% Pin Locking • Up to 360 User-Programmable I/O Pins • 4,024 Flip-Flops • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with