64WORD Search Results

KCP 357

Contextual Info: S-2911R/I CMOS 1K-bit serial E2PROM Gl code The S-2911R /I is a high speed, low power lK -b it E2PROM th a t uses th e CMOS flo atin g -g ate process. E ither 64word X 16-bit or 128-w ordX 8-bit can be selected . It is read or w ritten serially. Features W rite operation with built-in tim e r

64-Word

Contextual Info: SEIKO INSTRUMENTS U S A BTE Ö123443 D DGOGSSl T « S E I J S-2911R/I { C M O S 1K-bit sériai E2PROM Gl code The S-2911R/I is a high speed, low power lK -b it E2pROM th a t uses th e CMOS flo atin g -g ate process. E ither 64wordX 16-bit or 128-w ordX 8-bit can be selected . It is

Non-Volatile RAM

Abstract: S-22H DP-018
Contextual Info: Rev.1.1 S-22 Series PARALLEL NON-VOLATILE RAM The S-22 Series is a non-volatile CMOS RAM, composed of a CMOS static RAM and a non-volatile electrically erasable and programmable 2 memory E PROM to backup the SRAM. The organization is 256wordx4-bit (total 1K bits) for the S-22H12 and the S-22S12, and 64word×4-bit (total 256 bits) for the S-22H10 and the S-22S10.

Contextual Info: S-93L46A/56A/66A LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM www.sii-ic.com Rev.7.0_00 Seiko Instruments Inc., 2004-2011 The S-93L46A/56A/66A is a low voltage operation, high speed, low current consumption, 3-wire serial E2PROM with a wide operating voltage range. The S-93L46A/56A/66A has the capacity of 1 K-bit, 2 K-bit and 4 K-bit, and the organization is 64word x 16-bit, 128-word × 16-bit, and 256-word × 16-bit. It is capable of sequential read, at which time addresses are

S-29171

Abstract: s2917if10 S-2917110 S2917I seiko 64 s chip
Contextual Info: I KO INSTRUMENTS U S A 3*1E ] • 0123^3 00DQSÔ3 T WSEIJ S-2917R/I CMOS 1K-bit serial E2PROM Easy interface with serial port The S-2917R/I is a high speed, low power lK - b it E2 PR O M that uses the CM OS floating-gate process. Eith er 64wordx 16-bit or 128-wordX8-bit can be selected. It is

S-93L46A

Abstract: S-93L56A S-93L66A 93l46 S93L66
Contextual Info: S-93L46A/56A/66A LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM www.sii-ic.com Rev.7.0_00 Seiko Instruments Inc., 2004-2011 The S-93L46A/56A/66A is a low voltage operation, high speed, low current consumption, 3-wire serial E2PROM with a wide operating voltage range. The S-93L46A/56A/66A has the capacity of 1 K-bit, 2 K-bit and 4 K-bit, and the organization is 64word x 16-bit, 128-word × 16-bit, and 256-word × 16-bit. It is capable of sequential read, at which time addresses are

Contextual Info: S-93L46A/56A/66A LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM www.sii-ic.com Rev.7.0_00 Seiko Instruments Inc., 2004-2011 The S-93L46A/56A/66A is a low voltage operation, high speed, low current consumption, 3-wire serial E2PROM with a wide operating voltage range. The S-93L46A/56A/66A has the capacity of 1 K-bit, 2 K-bit and 4 K-bit, and the organization is 64word x 16-bit, 128-word × 16-bit, and 256-word × 16-bit. It is capable of sequential read, at which time addresses are

MSM6252RS

Abstract: M6252 F3341 MSM6252
Contextual Info: J2W0034-27-X2 作成：1998年 1月 MSM6252 l 前回作成：1996年 7月 ¡ 電子デバイス MSM6252 64wordsx4Bit FIFO n 概要 MSM6252は，シリコンゲートCMOSを用いた64words×4 bits First In First Out Memoryで，Fairchild 3341 MOS FIFOとはコンパチブルでデータの入力 Shift In は非同期動作が可能です。またビットおよ

93l46

Contextual Info: S-93L46A/56A/66A LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM www.sii-ic.com Rev.8.0_00 Seiko Instruments Inc., 2004-2013 The S-93L46A/56A/66A is a low voltage operation, high speed, low current consumption, 3-wire serial E2PROM with a wide operating voltage range. The S-93L46A/56A/66A has the capacity of 1 K-bit, 2 K-bit and 4 K-bit, and the organization is 64word x 16-bit, 128-word × 16-bit, and 256-word × 16-bit. It is capable of sequential read, at which time addresses are

74635

Abstract: be-rz 2914r
Contextual Info: SEIKO INSTRUMENTS U S A 3=jE D B Ö153443 G0GD5S5 S * S E I J S-2914R/RF CMOS 1K-bit serial E2PROM NS code The S-2914R is a high speed, low pow er lK -b it E2PROM th a t uses the CMOS flo atin g -g ate process. E ither 64wordX 16-bit or 128-w ordX 8-bit can be selected . It is

Contextual Info: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 2 D −55°C to 125°C Operating Temperature D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance − SMJ320C30-40 (50-ns Cycle) 40 MFLOPS

AT91SAM3U4

Abstract: at91sam3 1N1308 MAR 735 REGULATOR IC 7912 pin identify AT91SAM3U4E SAM3u1 AT91SAM3U 3961 G.E 0x20180
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

Contextual Info: User’s Manual V850E/ME2 32-Bit Single-Chip Microcontroller Hardware µPD703111A Document No. U16031EJ3V0UD00 3rd edition Date Published June 2004 N CP(K) Printed in Japan [MEMO] 2 User’s Manual U16031EJ3V0UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Contextual Info: SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 D Processed to MIL-PRF-38535 QML D Operating Temperature Ranges: D D D D D D D D D D − Military (M) −55°C to 125°C − Special (S) −55°C to 105°C

MOTOROLA ONCORE UT plus

Abstract: hp 35821 6132 RAM 731 motorola MPCPRGREF/D LG E50 MPC8xx QMC SMC microcode MPC857DSL MPC857T MPC862
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MPC862UM/D 09/2002, REV 2 MPC862 PowerQUICC Family User’s Manual Supports MPC862P MPC862T MPC857T MPC857DSL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

18-BIT

Contextual Info: * SYNERGY FIFOs. SEM IC O N D U C TO R PAGE Ultra-High-Speed FIFOs SY69164 Ultra-High-Speed 1Kx24 FIFO. 9-2 SY69165 Ultra-High-Speed 3Kx8 FI FO . 9-3

KSC5601

Abstract: D8A1 KS0040 d6a1 16f7 1B60 H124 128X8 16X16 8X16
Contextual Info: KS0040 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD APRIL. 1999. KS0040 65COM/132SEG DRIVER & CONTROLLER FOR STN LCD KS0040 Specification Revision History Version 0.0 1.0 1.1 2 Content Original 1 Changed function MPU interface pin & method are changed.

LSI403LP

Contextual Info: Preliminary – Content Subject to Change LSI403LP Digital Signal Processor Preliminary Datasheet The LSI403LP is a 16-bit, fixed-point digital signal processor DSP based on the ZSP 400 DSP core. The LSI403LP contains an entire DSP system on a single chip, and is designed for applications requiring lower

Contextual Info: Spansion SLC NAND Flash Memory for Embedded 1 Gb, 2 Gb, 4 Gb Densities: 4-bit ECC, x8 and x16 I/O, 1.8V VCC S34MS01G2, S34MS02G2, S34MS04G2 Spansion® SLC NAND Flash Memory for Embedded Cover Sheet Data Sheet Preliminary Notice to Readers: This document states the current technical specifications regarding the Spansion

Contextual Info: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004 2 D −55°C to 125°C Operating Temperature D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance − SMJ320C30-40 (50-ns Cycle) 40 MFLOPS

Contextual Info: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H - FEBRUARY 1991 - REVISED JUNE 2004 2 D -55°C to 125°C Operating Temperature D Two 32-Bit External Ports D D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance - SMJ320C30-40 (50-ns Cycle)

Contextual Info: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H - FEBRUARY 1991 - REVISED JUNE 2004 2 D -55°C to 125°C Operating Temperature D Two 32-Bit External Ports D D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance - SMJ320C30-40 (50-ns Cycle)

Contextual Info: SMJ320C30 DIGITAL SIGNAL PROCESSOR SGUS014H - FEBRUARY 1991 - REVISED JUNE 2004 2 D -55°C to 125°C Operating Temperature D Two 32-Bit External Ports D D D D D D D D D D D D Range, QML Processing Processed to MIL-PRF-38535 QML Performance - SMJ320C30-40 (50-ns Cycle)

Contextual Info: Spansion SLC NAND Flash Memory for Embedded 1 Gb, 2 Gb, 4 Gb Densities: 4-bit ECC, x8 and x16 I/O, 3V VCC S34ML01G2, S34ML02G2, S34ML04G2 Spansion® SLC NAND Flash Memory for Embedded Cover Sheet Data Sheet Preliminary Notice to Readers: This document states the current technical specifications regarding the Spansion