670PS Search Results

Contextual Info: 2.5GHz ANY DIFF. IN-TO-LVPECL Precision Edge PROGRAMMABLE CLOCK DIVIDER/FANOUT SY89871U BUFFER WITH INTERNAL TERMINATION Final FEATURES DESCRIPTION • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by

Contextual Info: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES Precision Edge® ̈ Two matched-delay outputs: • Bank A: undivided pass-through QA

INTEL+2118+DRAM

Abstract: INTEL 2116 DRAM
Contextual Info: Intel Xeon® Processor 5500 Series Datasheet, Volume 2 April 2009 Order Number: 321322-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple PECL to ECL Translator MC100LVEL91 MC100EL91 The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard

rohde

Abstract: prbs noise generator TLK2521 TLK2521EVM
Contextual Info: SLLA149 – JULY 2003 Refclk Jitter Analysis for the TLK2521 The jitter on the reference clock GTXclk can be a very crucial factor when designing applications with the TLK2521. The TLK2521 has an internal PLL with a certain bandwidth depending on the data rate. Jitter on the Refclk with a frequency below the PLL bandwidth gets

SY89871U

Abstract: SY89871UMI SY89871UMITR SY89874U
Contextual Info: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL SY89871U Precision Edge™ PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel FEATURES • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by

SY89871U

Abstract: SY89871UMG SY89871UMGTR SY89871UMI SY89871UMITR
Contextual Info: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES Precision Edge® „ Two matched-delay outputs: • Bank A: undivided pass-through QA

LGA1366

Abstract: 2C41h LGA 1366 Intel socket 1366 PIN LAYOUT
Contextual Info: Intel Xeon® Processor 3500 Series Datasheet, Volume 2 March 2009 Document Number: 321344-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

Contextual Info: CXB1505Q-Y SONY. Triple Fan-Out Buffer with Common Enable and Differential Output_ Description The CXB1505Q-Y is an ultra high speed monolithic ECL IC, which contains three Line Drivers. Each driver has two paires of differential output pins QnA,

VT1315

Contextual Info: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by

LVEL91

Abstract: DL140 MC100EL91 MC100LVEL91 SE540 Nippon capacitors
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple PECL to ECL Translator The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard

SY89871U

Abstract: SY89871UMG SY89871UMGTR SY89871UMI SY89871UMITR
Contextual Info: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by

2c14h

Contextual Info: Intel Xeon® Processor 5500 Series Datasheet, Volume 2 April 2009 Order Number: 321322-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

Contextual Info: 2.5GHz ANY DIFF. IN-TO-LVPECL Precision Edge PROGRAMMABLE CLOCK DIVIDER/FANOUT SY89871U FINAL BUFFER WITH INTERNAL TERMINATION FEATURES • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by 2, 4, 8, 16 > (QB0, QB1)

Nippon capacitors

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple PECL to ECL Translator The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard

LVEL91

Abstract: Nippon capacitors
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple PECL to ECL Translator The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard

Contextual Info: SY89871U 2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer w/ Internal Termination General Description The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input AC or DC-coupled CML, LVPECL, HSTL or

LT1357

Abstract: LT1360 LT1363 LT1395 LT1812 LT1815
Contextual Info: DESIGN FEATURES LT1815: 220MHz, 1500V/µs Amplifier Saves Space and Power by Kris Lokere Introduction The LT1815 is a low power, low distortion single op amp with a 220MHz gain bandwidth product and a 1500V/ µs slew rate. The device operates with supplies from ±2V to ±6V and draws