676FBGA Search Results

rdl 117-a

Abstract: pa-1000b
Contextual Info: A d v a n c e d v O .7 ? TM P r o A S IC ^ F la s h F a m ily F P G A s High Performance, Low Skew, Splitable Global Network 100% Routability and Utilization I/O Schmitt-Trigger Option on Every Input Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate

Contextual Info: v2.0  ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

484-FBGA

Abstract: 484FBGA 256-FBGA LB 1 39K250
Contextual Info: Delta39K ISR™ CPLD Family ADVANCE INFORMATION CPLDs at FPGA Densities™ • Multiple I/O standards supported — LVCMOS, LVTTL, PCI, SSTL, HSTL, and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs • Programmable slew rate control on each I/O pin

gl324

Abstract: 180 nm CMOS standard cell library AMI 198kB ProASICPLUS Flash Family FPGAs v3.2 APA075
Contextual Info: v3.2 TM ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

JC 201 SC

Abstract: GL324 ProASICPLUS Flash Family FPGAs v3.1
Contextual Info: v3.1 TM ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts • 100% Routability and Utilization High C apaci t y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy

GL324

Abstract: ads pa-600 ups 400 ec
Contextual Info: v3.3 TM ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts • 100% Routability and Utilization High C apaci t y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy

ACTEL proASIC PLUS

Abstract: RAM256X9SST APA150 FIFO256X9SST ACTEL proASIC PLUS APA450
Contextual Info: v2.0  ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

84 FBGA

Abstract: 39K100 39K200 39K30 39K50 388-BGA
Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs

8kx1 RAM

Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs

39k200

Abstract: CY39200V
Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs

CY39100V484B-125BBI

Abstract: programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K165 39K30 39K50 CY39100V208B-125NTC
Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

schematic diagram ups 600 actel silicon sculptor

Abstract: FLASHPRO LITE GL324 ProASICPLUS Flash Family FPGAs v3.0 W5108 GL25 APA075 APA150 APA300 APA600
Contextual Info: v3.0 TM ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts • 100% Routability and Utilization High C apaci t y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy

220v AC voltage stabilizer schematic diagram

Abstract: LG color tv Circuit Diagram tda 9370 1000w inverter PURE SINE WAVE schematic diagram schematic diagram atx Power supply 500w TV SHARP IC TDA 9381 PS circuit diagram wireless spy camera 9744 mini mainboard v1.2 sony 279-87 transistor E 13005-2 superpro lx
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 AD9272 Analog Front End, iMEMS Accelerometers & Gyroscopes . . . . . . 782, 2583 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-528 Acceleration and Pressure Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2585

CY39200V

Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin

XC3S250E design guide

Abstract: XC3S400-4FTG256C XC3S50AN-4TQG144C XC2S600E-6FGG456C XC5VSX50T-1FFG1136C HW-SPAR3E-SK-UNI-G XC3S1400A-4FGG484C XC3S400A-4FTG256C XC2C256-TQ144 XC3S400AN-4FGG400C
Contextual Info: Spartan and Virtex Field Programmable Gate Arrays The Spartan-3 FPGA family features a broad range of densities, general functionality and targeted specific application solutions. Spartan-3A DSP: • DSP Optimized • Ideal for applications where integrated DSP MACs and expanded memory

delta39k

Abstract: 39K100 39K30 39K50
Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

p21 transistor

Abstract: PECLR ACTEL proASIC PLUS APA450
Contextual Info: v2.0  ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

ACTEL proASIC PLUS

Abstract: ACTEL proASIC PLUS APA450 ProASIC PLUS v0.1
Contextual Info: v2.0  ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

RAM256X9SST

Abstract: ProASIC PLUS v0.1
Contextual Info: Advanced v0.6 ProASICPLUS Family Flash FPGAs Fe a t ur es an d B e ne f i ts I/O High C apaci t y • Schmitt Trigger option on Every Input • Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate • Bidirectional Global I/Os • Compliance with PCI Specification Revision 2.2

Contextual Info: Advanced v0.7  ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts • High Performance, Low Skew, Splitable Global Network • 100% Routability and Utilization High C apaci t y • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM

Contextual Info: v2.0  ProASICPLUS Flash Family FPGAs F ea t u re s an d B e n e fi t s • 100% Routability and Utilization H ig h C a p ac it y I/O • 75,000 to 1 million System Gates • 27k to 198kbits of Two-Port SRAM • 66 to 712 User I/Os Re pr og ra mm a b le Fl as h T ec h no lo g y

delta39k

Abstract: 39K100 39K165 39K30 39K50 CY3LV010 CY39200V
Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs