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Festo NPHS-S6-M-G38 (8059259) Coupling Plug, pneu, 10 bar, G3/8 male thrd
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	NPHS-S6-M-G38 (8059259)	Bulk	10		1	1 $6.38 10 $6.38 100 $6.38 1000 $6.38 10000 $6.38	Buy Now
Festo NPHS-D6-M-G38 (8059276) Coupling Socket, pneu, 20 bar, 2050 L/min, G3/8 male thrd
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	NPHS-D6-M-G38 (8059276)	Bulk			1	1 $64.44 10 $64.44 100 $64.44 1000 $64.44 10000 $64.44	Get Quote
Festo VUWS-LT30-M52-M-G38 (8096576) Valve, pneu actuated, poppet, 5/2 monostable, inline, G3/8, sz 30
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	VUWS-LT30-M52-M-G38 (8096576)	Bulk			1	1 $102.01 10 $102.01 100 $102.01 1000 $102.01 10000 $102.01	Get Quote
Festo VUWS-LT30-T32C-M-G38 (8036706) Valve, pneu actuated, poppet, 2x3/2 NC, inline, G3/8, sz 30
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	VUWS-LT30-T32C-M-G38 (8036706)	Bulk			1	1 $106.26 10 $106.26 100 $106.26 1000 $106.26 10000 $106.26	Get Quote
Festo VUWS-LT30-M32C-M-G38 (8096574) Valve, pneu actuated, poppet, 3/2 NC, inline, G3/8, sz 30
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	VUWS-LT30-M32C-M-G38 (8096574)	Bulk			1	1 $85.01 10 $85.01 100 $85.01 1000 $85.01 10000 $85.01	Get Quote

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MG388 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39Kâ 64-bit 39K200-208EQFP 39K165 39K200 -233MHz Delta39K165Z 144-FBGA	PDF
84 FBGA Abstract: 39K100 39K200 39K30 39K50 388-BGA Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 66-MHz 64-bit 39K165 208-EQFP, 484-FBGA, 388-BGA, 676-FBGA 84 FBGA 39K100 39K200 39K30 39K50 388-BGA	PDF
8kx1 RAM Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 233-MHz MIL-STD-883" /JESD22A114-A 39K50 39K30 Delta39K 39K165/200 CY3LV002 CY3LV020. 8kx1 RAM	PDF
39k200 Abstract: CY39200V Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 250-MHz 39k200 CY39200V	PDF
CY39100V484B-125BBI Abstract: programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K165 39K30 39K50 CY39100V208B-125NTC Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39KTM 66-MHz 64-bit 39K165 MG388 CY39030 -256FBGA CY39100V484B-125BBI programmable slew rate control IO AT17LV010-10JI CY39030V256-125MBC IO1 5V 39K100 39K30 39K50 CY39100V208B-125NTC	PDF
39K100 Abstract: 39K30 39K50 Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features — Clock polarity control at each register • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2	Original	Delta39KTM 64-bit 39K200-208EQFP 39K165 39K200 -233MHz Delta39K165Z 39K100 39K30 39K50	PDF
CY39200V Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin	Original	Delta39KTM NT208 51-85069-B 388-Lead MG388 256-Ball BB256/MB256 1-85108-A CY39200V	PDF
delta39k Abstract: 39K100 39K30 39K50 Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39KTM 64-bit 39K165 MG388 CY39030 -256FBGA delta39k 39K100 39K30 39K50	PDF
delta39k Abstract: 39K100 39K165 39K30 39K50 CY3LV010 CY39200V Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 64-bit Delta39K 39K165/200 CY3LV002 CY3LV020. Delta39K. 39K100 39K165 39K30 39K50 CY3LV010 CY39200V	PDF
bga 484 0.8mm pitch Abstract: 20532 tqfp 39K100 39K200 39K30 39K50 484FBGA CY39200V208-181NTXC CY39100V208B-125NTxC cy39030v208-125ntxc Contextual Info: Delta39K ISR™ CPLD Family CPLDs at FPGA Densities™ Features • Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs	Original	Delta39KTM 66-MHz 64-bit 39K165 208-EQFP, 484-FBGA, 388-BGA, 676-FBGA bga 484 0.8mm pitch 20532 tqfp 39K100 39K200 39K30 39K50 484FBGA CY39200V208-181NTXC CY39100V208B-125NTxC cy39030v208-125ntxc	PDF
CY39100V484-125BBI Abstract: "Single-Port RAM" delta39k Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin	Original	Delta39KTM CY39100V484-125BBI "Single-Port RAM" delta39k	PDF
NT208 Abstract: 1kx8 rom 250NTC Contextual Info: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Carry-chain logic for fast and efficient arithmetic operations •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+	Original	Delta39KTM 250-MHz NT208 1kx8 rom 250NTC	PDF