74AUP1G04 Search Results

Contextual Info: 74AUP1G04 SINGLE INVERTER GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. Future Product The 74AUP1G04 is a single inverter gate with a standard push-pull

Contextual Info: 74AUP1Z04 Low-power X-tal driver with enable and internal resistor Rev. 5 — 9 August 2012 Product data sheet 1. General description The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in

74AUP1G04

Abstract: 74AUP1G04GM 74AUP1G04GW JESD22-A114-C MO-203
Contextual Info: 74AUP1G04 Low-power inverter Rev. 01 — 18 July 2005 Product data sheet 1. General description The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1Z04

Abstract: crystal 8mHZ 74AUP1G04 74AUP1GU04 74AUP1Z04GF 74AUP1Z04GM 74AUP1Z04GW NX5032GA 8MHZ crystal
Contextual Info: NXP’s AUP1Z04 Demo board Low-power crystal driver with enable and internal bias resistor The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in crystal oscillator applications.

Contextual Info: 74AUP1G04 Low-power inverter Rev. 7 — 27 June 2012 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP1G04 Low-power inverter Rev. 6 — 14 February 2012 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

74AUP1G04

Abstract: 74AUP1GU04 74AUP1Z04 74AUP1Z04GF 74AUP1Z04GM 74AUP1Z04GW
Contextual Info: 74AUP1Z04 Low-power X-tal driver with enable and internal resistor Rev. 3 — 22 July 2010 Product data sheet 1. General description The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in

Contextual Info: 74AUP1G04 Low-power inverter Rev. 5 — 5 December 2011 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP1Z04 Low-power X-tal driver with enable and internal resistor Rev. 5 — 9 August 2012 Product data sheet 1. General description The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in

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Abstract: SOT-665 74AUP1G04 74AUPG04DTR 74AUPG04GTR A115-A C101
Contextual Info: 74AUP1G04 Low power single inverter gate Features • High speed: tPD = 4.3 ns max. at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■ Low power dissipation:

74AUP1G04

Abstract: 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW JESD22-A114-C MO-203
Contextual Info: 74AUP1G04 Low-power inverter Rev. 02 — 28 June 2006 Product data sheet 1. General description The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G04

Abstract: 74AUP1GU04 74AUP1Z04 74AUP1Z04GF 74AUP1Z04GM 74AUP1Z04GW JESD22-A114E
Contextual Info: 74AUP1Z04 Low-power X-tal driver with enable and internal resistor Rev. 02 — 3 July 2008 Product data sheet 1. General description The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in

74AUP1G04

Abstract: 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW 74AUP1G04GV
Contextual Info: 74AUP1G04 Low-power inverter Rev. 03 — 5 November 2009 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP1Z04 Low-power X-tal driver with enable and internal resistor Rev. 4 — 1 December 2011 Product data sheet 1. General description The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with enable circuitry and an internal bias resistor to provide a device optimized for use in

74AUP1G04

Abstract: 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW
Contextual Info: 74AUP1G04 Low-power inverter Rev. 4 — 30 June 2010 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP1G04-Q100 Low-power inverter Rev. 1 — 18 November 2013 Product data sheet 1. General description The 74AUP1G04-Q100 provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

001aaf022

Contextual Info: 74AUP1G04 Low-power inverter Rev. 02.00 — 16 May 2006 Product data sheet 1. General description The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

Contextual Info: 74AUP1G04 SINGLE INVERTER GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable ( Top View ) applications. ( Top View ) 5 Vcc NC 1 The 74AUP1G04 is a single inverter gate with a standard push-pull

Contextual Info: 74AUP1G04 Low-power inverter Rev. 7 — 27 June 2012 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP1G04 Low power single inverter gate Features • High speed: tPD = 4.3 ns max. at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■ Low power dissipation:

Contextual Info: 74AUP1G04 Low power single inverter gate Features • High speed: tPD = 4.3 ns max. at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■ Low power dissipation:

Contextual Info: 74AUP1G08 Low-power 2-input AND gate Rev. 5 — 12 April 2012 Product data sheet 1. General description The 74AUP1G08 provides the single 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

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Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

Contextual Info: 74AUP1G08 Low-power 2-input AND gate Rev. 6 — 22 June 2012 Product data sheet 1. General description The 74AUP1G08 provides the single 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.