74AUP1G04GM Search Results

74AUP1G04

Abstract: 74AUP1G04GM 74AUP1G04GW JESD22-A114-C MO-203
Contextual Info: 74AUP1G04 Low-power inverter Rev. 01 — 18 July 2005 Product data sheet 1. General description The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

SOT-353

Contextual Info: NPA Number 022 September 2012 New Product Announcement Announcement LOGIC Advanced Ultra-Low Power Logic 74AUP1Gxx Description Advanced Ultra Low Power CMOS Single Gate Logic • 0.8 V to 3.6 V • 4 ma drive capability at 3.0 V  7 ns typical propagation time at 3V

Contextual Info: 74AUP1G04 Low-power inverter Rev. 7 — 27 June 2012 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP1G04 Low-power inverter Rev. 6 — 14 February 2012 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP1G04 Low-power inverter Rev. 5 — 5 December 2011 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

74AUP1G04

Abstract: 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW JESD22-A114-C MO-203
Contextual Info: 74AUP1G04 Low-power inverter Rev. 02 — 28 June 2006 Product data sheet 1. General description The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

74AUP1G04

Abstract: 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW 74AUP1G04GV
Contextual Info: 74AUP1G04 Low-power inverter Rev. 03 — 5 November 2009 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

74AUP1G04

Abstract: 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW
Contextual Info: 74AUP1G04 Low-power inverter Rev. 4 — 30 June 2010 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

001aaf022

Contextual Info: 74AUP1G04 Low-power inverter Rev. 02.00 — 16 May 2006 Product data sheet 1. General description The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

Contextual Info: 74AUP1G04 Low-power inverter Rev. 7 — 27 June 2012 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.