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    74AUP2G80GD Price and Stock

    Rochester Electronics LLC 74AUP2G80GD,125

    IC FF D-TYPE DUAL 1BIT 8XSON
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    DigiKey 74AUP2G80GD,125 Bulk 2,049
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    NXP Semiconductors 74AUP2G80GD,125

    Flip Flop D-Type Pos-Edge 2-Element Automotive 8-Pin XSON T/R
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    Verical 74AUP2G80GD,125 173,800 2,507
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    74AUP2G80GD,125 2,811 2,507
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    Rochester Electronics 74AUP2G80GD,125 176,611 1
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    74AUP2G80GD Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74AUP2G80GD NXP Semiconductors Low-power dual D-type flip-flop; positive-edge trigger Original PDF
    74AUP2G80GD NXP Semiconductors 74AUP2G80 - IC AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO8, 3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2, SON-8, FF/Latch Original PDF
    74AUP2G80GD,125 NXP Semiconductors Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT996-2 (XSON8U); Container: Reel Pack, Reverse, Reverse Original PDF
    74AUP2G80GD,125 NXP Semiconductors 74AUP2G80 - IC AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8, 3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT-996-2, XSON-8, FF/Latch Original PDF

    74AUP2G80GD Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 8 — 21 January 2013 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock


    Original
    PDF 74AUP2G80 74AUP2G80

    74AUP2G80

    Abstract: 74AUP2G80DC 74AUP2G80GD 74AUP2G80GT JESD22-A114E JESD78
    Text: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 04 — 2 June 2008 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock


    Original
    PDF 74AUP2G80 74AUP2G80 74AUP2G80DC 74AUP2G80GD 74AUP2G80GT JESD22-A114E JESD78

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 6 — 7 December 2011 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock


    Original
    PDF 74AUP2G80 74AUP2G80

    74AUP2G80

    Abstract: 74AUP2G80DC 74AUP2G80GT JESD78
    Text: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 5 — 5 October 2010 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock


    Original
    PDF 74AUP2G80 74AUP2G80 74AUP2G80DC 74AUP2G80GT JESD78

    Untitled

    Abstract: No abstract text available
    Text: 74AUP2G80 Low-power dual D-type flip-flop; positive-edge trigger Rev. 7 — 14 June 2012 Product data sheet 1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock


    Original
    PDF 74AUP2G80 74AUP2G80