74HC109 Search Results
74HC109 Result Highlights (3)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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CD74HC109M |
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High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
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SN74HC109DRG4 |
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Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85 |
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CD74HC109E |
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High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
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74HC109 Price and Stock
Rochester Electronics LLC MC74HC109NIC FF JK TYPE DBL 1-BIT 16-PDIP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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MC74HC109N | Bulk | 63,000 | 1,150 |
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Rochester Electronics LLC 74HC109D,652IC FF JK TYPE DOUBLE 1BIT 16-SO |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HC109D,652 | Bulk | 55,250 | 1,310 |
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Rochester Electronics LLC SN74HC109DIC FF JK TYPE DBL 1-BIT 16-SOIC |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN74HC109D | Bulk | 37,562 | 515 |
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Rochester Electronics LLC CD74HC109EIC FF JK TYPE DBL 1-BIT 16-PDIP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC109E | Tube | 24,309 | 775 |
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Rochester Electronics LLC 74HC109FPEL-EIC FF JK TYPE DOUBLE 1-BIT |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HC109FPEL-E | Bulk | 22,000 | 310 |
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74HC109 Datasheets (23)
Part | ECAD Model | Manufacturer | Description | Curated | Datasheet Type | PDF Size | Page count | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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74HC109 |
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Dual J invertedK flip-flop with set and reset positive-edge trigger | Original | 57.64KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109 |
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positive-edge trigger | Original | 50KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109D |
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Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger | Original | 57.63KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109D | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109D,652 |
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Bulk Pack, CECC | Original | 57.61KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109D,653 |
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13", CECC | Original | 57.61KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109D/AUJ |
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Logic - Flip Flops, Integrated Circuits (ICs), IC FLIP FLOP DUAL J-K 16SOIC | Original | 9 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109DB |
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Dual J inverted(K) flip-flop with set and reset, positive-edge trigger | Original | 67.49KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109DB | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109DB,112 |
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Tube | Original | 57.61KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109DB,118 |
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" | Original | 57.61KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109DB-T |
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V | Original | 57.61KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109DB-T | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109D-Q100J |
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Uncategorized - Miscellaneous - 74HC109D-Q100/SOT109/SO16 | Original | 790.33KB | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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74HC109D-T |
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V | Original | 57.61KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109D-T | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109DW |
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Dual J inverted(K) flip-flop with set and reset, positive-edge trigger | Original | 67.49KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109N |
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Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger | Original | 57.63KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109N | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HC109N,652 |
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT38-4 (DIP16); Container: Bulk Pack, CECC | Original | 57.61KB | 9 |
74HC109 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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74HC109Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features |
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CD54/74HC109, CD54/74HCT109 SCHS140A HC109 HCT109 SCLA008 SZZU001B, SDYU001N, SCET004, SCAU001A, 74HC109 | |
74HC109
Abstract: M74HC109 54HC 74HC M54HC109
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OCR Scan |
M54HC109 M74HC109 54/74LS109 M54/74HC109 M54/74HC109 S-10170 74HC109 M74HC109 54HC 74HC | |
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140B Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised December 2002 |
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CD54/74HC109, CD54/74HCT109 SCHS140B HC109 HCT109 CD74H CT109) 8415001EA CD54HC109F3A | |
HCT109 harris
Abstract: 74HCT109
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CD74H CT109) CD54/74HC109, CD54/74HCT109 SCHS140A HC109 HCT109 HCT109 harris 74HCT109 | |
CD74HC109E
Abstract: HC109 C109 CD54HC109F3A CD54HCT109F3A
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CD74H CT109) CD54/74HC109, CD54/74HCT109 SCHS140B HC109 HCT109 CD74HC109E C109 CD54HC109F3A CD54HCT109F3A | |
Contextual Info: blE J> MOTOROLA SC LOGIC MOTOROLA b3b72SS OCHlTBb T33 inom • SEMICONDUCTOR TECHNICAL DATA MC54/74HC109 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS T he MC54/74HC109 is id en tic a l in p in o u t to th e LS109. T he device in p u ts are |
OCR Scan |
b3b72SS MC54/74HC109 MC54/74HC109 LS109. 54/74H | |
Contextual Info: MOTOROLA SE M IC O N D U C TO R TECHNICAL DATA MC54/74HC109 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620*09 High-Performance Silicon-Gate CMOS T h e M C 5 4 /7 4 H C 1 0 9 is id e n tic a l in p in o u t to th e L S 1 0 9 . T h e d e v ic e in p u ts are |
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MC54/74HC109 | |
Contextual Info: - Technical Data File N um b er 1667 CD54/74HC109 C D54/74HCT109 High-Speed CMOS Logic Duai J-K Flip-Flop with Set and Reset Type Features: 9 2 C S -36532 • Positive-Edge triggered • A s y n c h ro n o u s S et a n d Reset m 60 M Hz Typical M axim um C lo ck Frequency |
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CD54/74HC109 D54/74HCT109 54/74H 92CS-38533R2 92CS-38534R2 92CS-38535R2 | |
G0175Contextual Info: Technical Data File N um ber CD54/74HC109 CD54/74HCT109 T-HL'-Q'l -01 1667 High-Speed CMOS Logic HARR IS S E M I C O N D S E CT OR to 27E D B 4 3 0 2 27 1 0 D 1 7 S M b 2 • HAS Dual J-K Flip-Flop with Set and Reset T yp e Features: 2J 2 K -H 2C P 12 VCC = 1 0 |
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CD54/74HC109 CD54/74HCT109 92CS-38S3Z 54/74H 92CS-38533R2 92CS-38535R2 G0175 | |
CXXXNContextual Info: MOTOROLA SC -CLOGIC} 02 b3b72Sa 0000170 5 ~T-4:b-07 -ü -7 MOTOROLA S E M IC O N D U C T O R TECHNICAL DATA MC54/74HC109 D ual J -K Flip-Flop w ith S e t and Reset J SUFFIX CERAM IC CA SE 620-09 High-Performance Silicon-Gate C M O S ' The M C 54/74H C 109 is identical in pinout to the LS109. The device inputs are |
OCR Scan |
b3b72Sa MC54/74HC109 54/74H LS109. CHC109 CXXXN | |
Contextual Info: •Technical Data File Number 1667 CD54/74HC109 C D54/74H CT109 High-Speed CMOS Logic Dual J-K Flip-Flop with Set and Reset Type Features: 92 CS -385*2 ■ Positive-Edge triggered • Asynchronous Set and Reset ■ 60 MHz Typical Maximum Clock Frequency @ Vcc - 5 V, C l = 15 pF, n = 25° C |
OCR Scan |
CD54/74HC109 D54/74H CT109 RCA-CD54/74HC109 CD54/74HCT109 92CS-38533R2 2CS-33534R2 92CS-38535R2 | |
Contextual Info: GD54/74HC109, GD54/74HCT109 DUAL J-K FLIP-FLOPS W ITH PRESET & CLEAR General Description are identical in pinout with individual J, K, Clock, Preset, to Pin Configuration the flip-flops and Clear U IC L R p T inputs. T h e s e flip-flops are e d g e sensitive to the |
OCR Scan |
GD54/74HC109, GD54/74HCT109 | |
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC109 Dual J-K Flip-Flop with Set and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS T he M C 54/74H C 10 9 is iden tical in p in o u t to th e LS109. The device in p u ts are N SUFFIX PLASTIC |
OCR Scan |
MC54/74HC109 54/74H LS109. | |
Contextual Info: G E SOLID STATE Dl D E I BÛ7SDÛ1 001152b 1 • -Technical Data File Number 0 1 -0 1 1667 CD54/74HC109 CD54/74HGT109 High-Speed CMOS Logic Dual J-K Flip-Flop with Set and Reset Type Features: 92CS-38532 ■ Positive-Edge triggered ■ Asynchronous Set and Reset |
OCR Scan |
001152b CD54/74HC109 CD54/74HGT109 92CS-38532 RCA-CD54/74HC109 CD54/74HCT109 92CS-38533R2 92CS-38534R2 38535R | |
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5555 FAIRCHILD optocoupler
Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
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SCYB017A A010203 5555 FAIRCHILD optocoupler MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N | |
74HC9046
Abstract: 74HCT4050 74hct7014 74HCT4049 74HC7541 74hct133 74HC9046A 74HC90 74HCT4059 74HC5555
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74HCU04 74HCTU04 74HC00 74HCT00 74HC02 74HCT02 74HC03 74HCT03 74HC04 74HC86 74HC9046 74HCT4050 74hct7014 74HCT4049 74HC7541 74hct133 74HC9046A 74HC90 74HCT4059 74HC5555 | |
k2645
Abstract: k4005 U664B mosfet k4005 MB8719 transistor mosfet k4004 SN16880N stk5392 STR451 BC417
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MK135 MK136 MK137 MK138 MK139 MK140 Mk142 MK145 MK155 157kr k2645 k4005 U664B mosfet k4005 MB8719 transistor mosfet k4004 SN16880N stk5392 STR451 BC417 | |
schematic diagram atx Power supply 500w
Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
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P462-ND P463-ND LNG295LFCP2U LNG395MFTP5U US2011) schematic diagram atx Power supply 500w pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS | |
FSQ510 Equivalent
Abstract: BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2
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GP-20) FSQ510 Equivalent BTA12 6008 bta16 6008 ZIGBEE interface with AVR ATmega16 Precision triac control thermostat thyristor t 558 f eupec gw 5819 diode transistor a564 A564 transistor BSM25GP120 b2 | |
freescale h01
Abstract: 74hc04a A638AN U15C 74HC04 74HC163A 74HC595A U15B AN1687 74HC163
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AN1687/D AN1687 RS-232 MC33411 freescale h01 74hc04a A638AN U15C 74HC04 74HC163A 74HC595A U15B AN1687 74HC163 | |
BUK2114
Abstract: BUK2114-50SYTS saa7117 SAA7136E MPSA92 168 saa7136 buk2914-50syts TDA8920BTH bu4508dx KMZ52
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1N4148 1N4531 1N47xxA 1PS10SB62 1PS10SB63 1PS10SB82 1PS181 1PS184 1PS193 1PS226 BUK2114 BUK2114-50SYTS saa7117 SAA7136E MPSA92 168 saa7136 buk2914-50syts TDA8920BTH bu4508dx KMZ52 | |
74HC9046
Abstract: 74hct4050 74HC273 CMOS TTL Logic Family Specifications 74hc245 74HCT297 74hc154 application 74hct133 74hc297 application notes 74HC7014 74HCT299
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OT27-1 OT38-4 OT146-1 OT101-1 OT222-1 OT117-1 74HCU 74HCT 74HC9046 74hct4050 74HC273 CMOS TTL Logic Family Specifications 74hc245 74HCT297 74hc154 application 74hct133 74hc297 application notes 74HC7014 74HCT299 | |
74HC109PContextual Info: MITSUBISHI HIGH S P E E D CMOS M 74H C 109P /FP /D P DUAL i-K F L I P - F L O P WITH S E T AND R E S E T DESCRIPTION T h e M 7 4 H C 1 0 9 is a s e m ic o n d u c to r in te g r a te d c irc u it c o n PIN CONFIGURATION TOP VIEW s is tin g of tw o p o s it iv e -e d g e t r ig g e r e d J - K flip flo p s w ith in |
OCR Scan |
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74hc109m
Abstract: 74HC109 74HC109B1R M74HC109
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OCR Scan |
M54HC109 M74HC109 54/74LS109 M54/74HC109 M54/M74HC109 S-1C170 00S44A3 74hc109m 74HC109 74HC109B1R M74HC109 |