74HCT27 Search Results

74HC27

Abstract: dhvqfn14 74HC27N 74HC27BQ 74HC27D 74HC27DB 74HC27PW 74HCT27 JESD22-A114E HCT273
Contextual Info: 74HC27; 74HCT27 Triple 3-input NOR gate Rev. 03 — 7 January 2008 Product data sheet 1. General description The 74HC27; 74HCT27 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL LSTTL . The 74HC27; 74HCT27 provides the 3-input NOR function.

Contextual Info: Technical Data CD54/74HC273 CD54/74HCT273 File Number 1479 High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Common clock and asynchronous master reset ■ Positive-edge triggering ■ Buffered inputs ■ Typical fmat — 60 MHz @ Vcc ~ 5 V, C l = 15pF, 7a = 25° C

74hc273

Abstract: harris hct273
Contextual Info: [ /Title CD74 HC273 , CD74 HCT27 3 /Subject (High Speed CMOS Logic Octal DType Flip- CD54/74HC273, CD54/74HCT273 Data sheet acquired from Harris Semiconductor SCHS174A High Speed CMOS Logic Octal D-Type Flip-Flop with Reset February 1998 - Revised May 2000

Contextual Info: 74HC27; 74HCT27 Triple 3-input NOR gate Rev. 03 — 7 January 2008 Product data sheet 1. General description The 74HC27; 74HCT27 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL LSTTL . The 74HC27; 74HCT27 provides the 3-input NOR function.

74HC273

Abstract: 74HCT273
Contextual Info: G E SOLI» STATE 01 D E | 3Û7S0Ô1 001175=1 4 Technical Data. T-46-07-05 CD54/74HC273 CD54/74HCT273 File Number 1479 High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Common clock and asynchronous master reset ■ Positive-edge triggering

Contextual Info: GD54/74HC273, GD54/74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH COMMON CLOCK & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 2 7 3 . They consist of eight master/slave D- Pin Configuration type flip-flops with a common Clock and common

Contextual Info: [ /Title CD74 HC27, CD74 HCT27 /Subject (High Speed CMOS Logic CD54/74HC27, CD54/74HCT27 Data sheet acquired from Harris Semiconductor SCHS132A High Speed CMOS Logic Triple 3-Input NOR Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs

74HC27

Contextual Info: Technical Data CD54/74HC27 CD54/74HCT27 File Number 1648 High-Speed CMOS Logic - V cc Triple 3-Input NOR Gate Type Features: • Buffered Inputs ■ Typical CD54/74HC27 Propagation Delay = 7ns @ l/cc = 5v, CL= 15pF. Ta = 25° C FUNCTIONAL DIAGRAM AND TERMINAL ASSIGNMENT

74HC273

Abstract: 74hct273 74LS273 74HC GD74HC273 pin diagram of 74ls273 GD74HC27 OT273
Contextual Info: GD54/74HC273, GD54/74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH COMMON CLOCK & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 2 7 3 . They consist of eight master/slave D- Pin Configuration type flip-flops with a common Clock and common

74HC273

Abstract: 74hct273
Contextual Info: [ /Title CD74 HC273 , CD74 HCT27 3 /Subject (High Speed CMOS Logic Octal DType Flip- CD54/74HC273, CD54/74HCT273 Data sheet acquired from Harris Semiconductor SCHS174A High Speed CMOS Logic Octal D-Type Flip-Flop with Reset February 1998 - Revised May 2000

54HCT273

Abstract: 74HCT273 J131 D FLIPFLOP PIN CONFIGURATION flip-flop 74HCT 74SC273 flip-flop JT
Contextual Info: ^ S u p e r Z e x in c . HCT/SC273 O '.ta i D F lip F lo p W it h C le a r »Preliminary Military 54HCT High Speed (74HCT) Standard (74SC) Octal D flip-flop with Clear 74HCT273 74SC273 54HCT273 Operating temperature range ( ° C) - 4 0 to + 8 5 - 4 0 to + 8 5

Contextual Info: GD54/74HC27, GD54/74HCT27 TRIPLE 3-INPUT NOR GATES General Description Pin Configuration These devices are identical in pinout to the 5 4 /7 4 L S 2 7 . They contain three independent 3-input NOR gates. These devices are characteriz­ ed for operation over wide temperature ranges to

74hc273

Abstract: 54HC273 74HCT273
Contextual Info: Technical Data, CD54/74HC273 CD54/74HCT273 File Number 1479 High-Speed CMOS Logic Octal D Flip-Flop with Reset Type Features: • Comm on clock and asynchronous master reset • Positive-edge triggering ■ Buffered inputs ■ Typical fm,K = 60 M H z 'SET

74HC273

Abstract: HCT273 74HC273N TSSOP20 Package 74HCT273 SO20 Package SSOP20 package 74HC273BQ 74HC273D 74HC273DB
Contextual Info: 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 — 24 January 2006 Product data sheet 1. General description The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL .

74hct273

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset with LSTTL Compatible Inputs MC54/74HCT273A High-Performance Silicon-Gate CMOS The M C54/74HCT273A may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs.

Contextual Info: Technical Data CD54/74HC27 CD54/74HCT27 File N um ber 1648 High-Speed CMOS Logic Triple 3-Input NOR Gate Type Features: • B uffered Inputs ■ Typical CD54/74HC27 P ropagation Delay = 7ns @ ^cc = 5v, Cl= 15pF, Ta = 25° C FUNCTIONAL DIAGRAM AND TERMINAL A SSIGNM ENT

T27b

Contextual Info: r z 7 S G S -T H O M S O N [j«M i[L i g im «S M 54HCT27 M 74HCT27 TRIPLE 3-INPUT NOR GATE • HIGHSPEED tpD = 9 ns (T Y P . A T V cc = 5 V . L O W P O W E R D IS S IP A T IO N Ice = 1 HA (M AX.) A T Ta = 2 5 C m C O M P A T IB L E W IT H T T L O U T P U T S

Contextual Info: 74HC273-Q100; 74HCT273-Q100 Octal D-type flip-flop with reset; positive-edge trigger Rev. 1 — 19 June 2013 Product data sheet 1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock CP and master reset (MR) inputs. The outputs Qn assume the

harris 74hct27

Abstract: CD54HC27F3A CD54HCT27F3A CD74HC27E CD74HC27M CD74HCT27E
Contextual Info: [ /Title CD74 HC27, CD74 HCT27 /Subject (High Speed CMOS Logic CD54/74HC27, CD54/74HCT27 Data sheet acquired from Harris Semiconductor SCHS132A High Speed CMOS Logic Triple 3-Input NOR Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs

74HC27

Abstract: 74HCT27P
Contextual Info: 74HC27; 74HCT27 Triple 3-input NOR gate Rev. 4 — 5 June 2013 Product data sheet 1. General description The 74HC27; 74HCT27 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of

74HC27

Contextual Info: HARRIS SEMICOND SECTOR 27E D • 4302571 00174=15 0 ■¡HAS Technical D _ CD54/74HC27 CD54/74HCT27 File Number 1648 T~- 4 3 'X i- O O High-Speed CMOS Logic Triple 3-Input NOR Gate

74hc273

Abstract: 74HCT273
Contextual Info: Technical Data CD54/74HC273 CD54/74HCT273 File Number 1 4 7 9 .1 High-Speed CMOS Logic Octal D Flip-Flop with Reset CLOCK CP “ D 2- -QO - 01 -02 03- -0 3 00□I - DATA _ IN P U T S 04- -0 4 05- -0 5 06- -0 6 07- -0 7 RESET TTR _ OATA O U TP U TS Type Feature*:

74HCT273

Abstract: j131 54HCT273 74HCT 74SC273 J13-1 D FLIPFLOP PIN CONFIGURATION
Contextual Info: ^ S u p e r Z e x in c . HCT/SC273 O '.ta i D F lip F lo p W it h C le a r »Preliminary Military 54HCT High Speed (74HCT) Standard (74SC) Octal D flip-flop with Clear 74HCT273 74SC273 54HCT273 Operating temperature range ( ° C) - 4 0 to + 8 5 - 4 0 to + 8 5

Contextual Info: 74HC27-Q100; 74HCT27-Q100 Triple 3-input NOR gate Rev. 1 — 3 June 2013 Product data sheet 1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in