74LS16 Search Results

74LS166A

Abstract: 54ls166a 54LS166
Contextual Info: SN54166, SN 54LS166A, SN74166. SN 74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS OCTOBER 1976 - REVISED MARCH 1988 S N 54166, S N 54LS 166A . . . J OR W PACKAGE S N 7416 6 . . . N PACKAGE S N 74LS 166A . . . D OR N PACKAGE • Synchronous Load • Direct Overriding Clear

74LS169A

Abstract: 74LS168A 74S168A S168A 74S169
Contextual Info: 74LS168A, 74LS169A, S168A, S169A Signetics 4-Bit Bidirectional Counters 4-Bit Up/Down Synchronous Counter Product Specification Logic Products FEATURES • Synchronous counting and loading • Up/down counting • Modulo 16 binary counter — '169A • BCD decade counter — ' 168A

74160PC

Abstract: 74LS160 parallel counter 74LS160PC BCD Decade logic diagram 74160 74LS160D 74LS162 74LS160DC 74160 74LS162 parallel counter logic diagram of 74ls160
Contextual Info: 160 162 • CO NN ECTIO N DIAGRAM / n i * 54/74160 54LS/74LS160 S4LS/74LS162 ^ ^ 4 /7 4 1 6 2 P IN O U T A \ / ô / o ô ï o / ^S Y N C H R O N O U S PRESETTABLE BCD DECADE COUNTERS DESC R IP TIO N — The ’160 and '162 are high speed synchronous decade

QE Logica 21

Abstract: 74ls164 74LS164 PIN DIAGRAM ad 440J AM25LS164DM 74ls gate symbols SN74LS164 74LS AM25LS164DC LS164
Contextual Info: Am25LS164 • Am54LS/74LS164 8-Bit Serial-ln, Parallel-Out Shift Register D IS T IN C T IV E C H A R A C T E R IS T IC S F U N C T I O N A L D E S C R IP T I O N • • T h e A m 2 5 L S 1 6 4 and A m 5 4 L S / 7 4 L S 1 64 are e ight-b it, serial in/parallel o u t sh ift registers bu ilt using advanced Low -Po w er

LS168A

Abstract: LS-168a LS168 sn74ls169an LS169A 74LS168 application note 25ls 74ls 74LS169A
Contextual Info: Am25LS168A • Am25LS169A Am54LS/74LS168A • Am54LS/74LS169A Synchronous Four-Bit Programmable Up-Down Counter F U N C T IO N A L D E S C R IP T IO N D IS T IN C T IV E C H A R A C T E R IS T IC S • • • • • A ll o p e ra tio n s are syn ch ro n o u s

74LS169DC

Abstract: 74LS169PC 74LS169D 74LS169 54LS169DM 54LS169FM 74LS169FC
Contextual Info: 169 C O N N E C T IO N D IA G R A M P IN O U T A 54LS/74LS169 O i o 4 cf & S Y N C H R O N O U S B I-D IR E C T IO N A L M O D U L O -1 6 BINARY C O U N T E R U /D [7 16] V cc CP |T 75] t c Po Î71 Qo Pi [ 7 T3J Qi P2 [ [ T2I o2 P 3 |T D E S C R IP T IO N — T he ’169 is a fu lly s y n c h ro n o u s 4 -sta g e u p /d o w n c o u n te r

Contextual Info: GD54/74LS164 8-BIT PARALLEL OUTPUT SERIAL SHIFT REGISTER Feature • • • Pin Configuration Gated Enable/Disable Serial Inputs Fully Buffered Clock and Serial Inputs Asynchronous Clear OUTPUTS Vcc Oh 14 13 12 11 10 Qh Qg Qf Qe CLEAR I Qf Qe CLEAR CLOCK

74ls166

Abstract: 74ls gate symbols 74LS TTL 74ls166 datasheet 74LS LS166 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS166 8-BIT SHIFT REGISTERS The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/ 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and

74LS163

Abstract: 74163 74s163 74LS163 74S163 LS163 54LS163
Contextual Info: 54/74163 4 位二进制同步计数器（同步清除） 简要说明 163 为可预置的 4 位二进制同步计数器，共有 54163/7416354S163/74S163， 54LS163/74LS163 三种线路结构形式。其主要电特性的典型值如下： 型号 fc PD

of ic 74166

Abstract: IC 74166
Contextual Info: SN54166, SN54LS166A, SN74166, 74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS O C T O B E R 197 6 - SN54166. SN 54LS166A • Sy n ch ro n o u s Load R E V IS E D M A R C H 1988 . . J OR W PACKAGE SN 74166 . . . N PACKAGE SN 74LS166A . . . D OR N PACKAGE • Direct Overriding Clear

74LS160D

Abstract: 74LS160PC IC 74LS160 74160PC 74LS160 parallel counter 74LS160P Ls 74160 74LS162D 74162FC logic diagram of 74ls160
Contextual Info: 160 • 162 CONNECTION DIAGRAM \ftoic oïb PINOUT A 54/74160 • 54LS/74LS160 ¿ ,6 ^ /7 4 1 6 2 • 94LS/74LS162 0/co4- / ^SYNCHRONOUS PRESETTABLE BCD DECADE COUNTERS H E îfilv c c C P |7 î ï DESCRIPTION — The ’160 and '162 are high speed synchronous decade

Contextual Info: GD54/74LS163A SYNCHRONOUS 4-BIT COUNTER: BINARY, SYNCHRONOUS CLEAR Feature • • • • • Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line • Diode-Clamped Inputs

Contextual Info: GD54/74LS161A SYNCHRONOUS 4 BIT COUNTERS; BINARY, DIRECT CLERAR Feature • • • • • • Pin Configuration Internal Look-Ahead for Fast Counting Carry Output tor n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs

74LS169A

Abstract: 74S168 74LS168A N74S168AN S168A 74S168A 74S169A N74LS168AN N74LS169AN N74S169AN
Contextual Info: Signetics 74LS168A, 74LS169A, S168A, S169A 4-Bit Bidirectional Counters 4-B it U p /D o w n Syn chron ou s C o un ter Logic Products FEATURES • S y n c h ro n o u s c o u n tin g and lo ad in g • U p /d o w n c o u n tin g • M o d u lo 16 b in a ry c o u n te r —

Contextual Info: MOTOROLA SN54/74LS168 SN54/74LS169 BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN 54/74LS 168 and SN 54/74LS 169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U /D input to control the direction

74ls169 motorola

Abstract: 8 decade counter
Contextual Info: g MOTOROLA SN54LS/74LS168 SN54LS/74LS169 D E S C R IP T IO N — Th eS N 54LS /7 4LS 16 8and S N 5 4LS /74 LS 169 are fully synchronous 4-stage u p /d o w n counters featuring a preset capability for programmable operation, carry lookahead for easy cas­

74LS165 ic PIN DIAGRAM

Contextual Info: GD54/74LS165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS WITH COMPLEMENTARY OUTPUTS Feature Pin Configuration • Com plem entary Outputs • D irect Overriding Load Data Inputs • G ated C lo ck Inputs • Parallel-to-Serial Data Conversion V c c INHIBIT' D R

Contextual Info: MITSUBISHI LSTTLs M 74LS164P 8 -B IT SER IA L-IN PARALLEL-OUT S H IFT REGISTER DESCRIPTION The M 74LS 164P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing an 8 -b it serial input-serial/parallel ou tp ut shift register fu nction w ith direct reset input.

S168A

Abstract: 74LS169A
Contextual Info: 74LS168A, 74LS169A, S168A, S169A S ig n e tic s 4-Bit Bidirectional Counters 4-Bit Up/Down Synchronous Counter Product Specification Logic Products FEATURES • Synchronous counting and loading • Up/down counting • Modulo 16 binary counter — '169A • BCD decade counter — '168A

74LS16

Contextual Info: GD54/74LS16 HEX INVERTED BUFFERS WITH OPEN-COLLECTOR OUTPUTS Features • High Output Voltage 1 5V • High Speed (tPD= 8 .5 n S typical) • Low Power Dissipation Pin Configuration Vcc 6A 6Y 4 13 2 5A 5Y 1 1 1 0 4A 4Y 9 8 Description Î> This device contains hex inverted buffers with open

74LS164

Abstract: 25LS164 QE Logica 21
Contextual Info: Am25LS164 • Am54LS/74LS164 8-Bit Serial-ln, Parallel-Out Shift Register D IS T IN C T IV E C H AR AC TER ISTIC S F U N C T IO N A L DESCRIPTION • • Gated serial inputs Asynchronous clear • A m 25LS devices o ffe r the follow ing improvements over A m 54/74 LS

54164

Abstract: IC 74164
Contextual Info: SN54164, SN 54LS164, SN74164, S N 74LS164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS MAR C H 1 9 7 4 - REVISED M AR C H 1988 Gated Serial Inputs S N 5 4 1 6 4 , S N 54 L S 1 6 4 . . . J OR W PACKAGE • Fully Buffered Clock and Serial Inputs S N 7 4 1 6 4 . . . N PACKAGE

M74LS160AP

Abstract: da qg 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 74LS160A P SYNCHRONOUS P R E S E T T A B L E DECADE COUNTER WITH D IRECT R E S E T DESCRIPTION The M 74LS160A P is a s e m ico n d u c to r in teg rated c irc u it PIN CONFIGURATION TOP VIEW c o n ta in in g a presettable synchronou s decade c o u n te r fu n c ­

Contextual Info: Am25LS160A/161A/162A/163A Am54LS/74LS160A/161 A/162A/163A Synchronous Four-Bit Counters L O G IC D IA G R A M S D IS T IN C T IV E C H A R A C T E R IS T IC S • • Synchronous presettable counters Decade 'L S 1 6 0 A and 'L S 1 6 2 A and binary ( ’L S 1 6 1 A a n d