74AC20 Search Results

74AC20

Abstract: 74AC20B 74AC20M 74AC20MTR 74AC20TTR TSSOP14
Contextual Info: 74AC20 DUAL 4-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:

74AC20SJ

Abstract: 74AC20 74AC20MTC 74AC20PC 74AC20SC AC20 M14A M14D MTC14 N14A
Contextual Info: Revised October 1998 74AC20 Dual 4-Input NAND Gate General Description Features • ICC reduced by 50% The AC20 contains four 4-input NAND gates. ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150” Narrow Body

Contextual Info: SGS-THOMSON 74AC20 M 0 gl3 l[LI(3ra [S!]D(BS DUAL 4-INPUT NAND GATE PRELIM IN ARY DATA . HIGH SPEED: tPD = 4 ns (TYP. atVcc =5V . LOW POWER DISSIPATION: Ice = 4 |xA (MAX.) at TA = 25 °C . HIGH NOISE IMMUNITY: V nih = V nil = 28% V cc (MIN.) . 50i2 TRANSMISSION LINE DRIVING

TSSOP14

Abstract: 74AC20 74AC20B 74AC20M 74AC20MTR 74AC20TTR
Contextual Info: 74AC20 DUAL 4-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:

TSSOP14

Abstract: 74AC20 74AC20B 74AC20M 74AC20MTR 74AC20TTR
Contextual Info: 74AC20 DUAL 4-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:

diode 36b3

Abstract: 74AC20 74AC20MTC 74AC20PC 74AC20SC 74AC20SJ AC20 M14A M14D MTC14
Contextual Info: Revised N ovem ber 1999 S E M IC D N D U C T O R T M 74AC20 Dual 4-Input NAND Gate General Description Features The AC 20 contains four 4-input NAND gates. • lc c reduced by 50% ■ O utputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description

Contextual Info: 01 S3 Semiconductor National ÆM 54AC/74AC20 Dual 4-Input NAND Gate General Description Features The 'AC20 contains lour 4-input NAND gates. • Ice reduced by 50% ■ Outputs source/sink 24 mA ■ Standard Military Drawing SMD — ’AC20: 5962-87613 OrderinQ Code: seesectione

Contextual Info: s e m ic o n d u c t o r Revised N ovem ber 1999 74AC20 Dual 4-Input NAND Gate General Description Features The AC 20 contains four 4-input NAND gates. • lc c reduced by 50% ■ O utputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description

74AC20

Abstract: 74AC20B 74AC20M 74AC20MTR 74AC20TTR AC20
Contextual Info: 74AC20 DUAL 4-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:

74AC20

Abstract: 74AC20MTC 74AC20PC 74AC20SC 74AC20SJ AC20 M14A M14D MTC14 N14A
Contextual Info: Revised November 1999 74AC20 Dual 4-Input NAND Gate General Description Features • ICC reduced by 50% The AC20 contains four 4-input NAND gates. ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150” Narrow Body

74AC20

Abstract: 74AC20MTC 74AC20PC 74AC20SC 74AC20SJ AC20 M14A M14D MTC14 N14A
Contextual Info: 74AC20 Dual 4-Input NAND Gate Features General Description • ICC reduced by 50% The AC20 contains four, 4-input NAND gates. ■ Outputs source/sink 24mA Ordering Information Order Number Package Number Package Description 74AC20SC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, 0.150" Narrow

Contextual Info: HARRIS SEMICOND SECTOR 37E 3 M3D2271 □ □ S S 3 C12 fl IHAS Technical D a ta _ T -M 3 -2 1 CD54/74AC20 CD54/74A C T20 1A Advance Information Dual 4-Input NAND Gate IB 1C 10 2A Type Features: • Typical propagation delay AC20 : 6 ns @ Vcc = 5 V, Ta - 25° C, C l = 50 pF

74AC20

Abstract: 74AC20MTC 74AC20PC 74AC20SC 74AC20SJ AC20 M14A M14D MTC14 N14A
Contextual Info: Revised February 2005 74AC20 Dual 4-Input NAND Gate General Description Features The AC20 contains four 4-input NAND gates. • ICC reduced by 50% ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Package Description Number 74AC20SC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, 0.150" Narrow

74AC20

Abstract: 74AC20MTC 74AC20PC 74AC20SC 74AC20SJ AC20 M14A M14D MTC14 U244
Contextual Info: R e v is e d O c to b e r 199 8 ï. < - •"? 74AC20 Dual 4-Input NAND Gate General Description Features T h e A C 2 0 c o n ta in s fo u r 4 -in p u t N A N D g a te s . ■ Iq q re d u c e d by 5 0 % ■ O u tp u ts s o u rc e /s in k 2 4 m A Ordering Code:

74AC20

Abstract: 74AC20B 74AC20M AC20
Contextual Info: 74AC20 DUAL 4-INPUT NAND GATE PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4 ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING

Contextual Info: 53 ÆM National Semiconductor 54AC/74AC20 Dual 4-Input NAND Gate General Description Features The 'AC20 contains four 4-input NAND gates. • Outputs source/sink 24 mA ■ Standard Military Drawing SMD — 'AC20: 5962-87613 Ordering Code: seesections Logic Symbol

Contextual Info: Revised O ctober 1998 S i i ; r : 3M & 74AC20 Dual 4-Input NAND Gate General Description Features The AC 20 contains fo u r 4-input NAND gates. • Ice reduced by 50% ■ O utputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description

Contextual Info: Technical Data_ CD54/74AC20 CD54/74ACT20 Advance Information Dual 4-Input NAND Gate Type Features: • Typical propagation delay AC20 : 6 ns @ l/cc = 5 V, r A = 25° C, CL = 50 pF FUNCTIONAL DIAGRAM & TERMINAL ASSIGNMENT The RCA CD54/74AC20 and CD54/74ACT20 dual 4-input

Contextual Info: Technical Data _ _ _ _ _ _ CD54/74AC20 CD54/74ACT20 1A Advance Information Dual 4-Input NAND Gate 1 B 1C 10 Type Features: • Typical propagation delay AC20 : 6 ns @ V'cc = 5 V, Ta = 25° C, CL = 50 pF FUNCTIONAL DIAGRAM & TERMINAL ASSIGNMENT The RCA CD54/74AC20 and CD54/74ACT20 dual 4-input

cd74ac20

Contextual Info: Technical D ata_ CD54/74AC20 CD54/74ACT20 Advance Information Dual 4-Input NAND Gate Type Features: • Typical propagation delay AC20 : 6 n s @ V c c = 5 V, 7» = 25° C, CL = 50 pF TERMINAL A SSIGNMENT The RCA CD54/74AC2Q and CD54/74ACT20 dual 4-input

Contextual Info: 74AC20 Dual 4-Input NAND Gate Features General Description • ICC reduced by 50% The AC20 contains four, 4-input NAND gates. ■ Outputs source/sink 24mA Ordering Information Order Number Package Number Package Description 74AC20SC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, 0.150" Narrow

Contextual Info: AC20 54AC/74AC20 Dual 4-Input NAND Gate Connection Diagrams ' Outputs Source/Sink 24 mA NC NC NC B S B 0 B Ordering Code: See Section 6 0 § s @@ NC NC NC Pin Assignment for LCC Pin Assignment for DIP, Flatpak and SOIC DC Characteristics unless otherwise specified

Contextual Info: AC20 54AC/74AC20 Dual 4-Input NAND Gate Connection Diagrams • Outputs Source/Sink 24 mA NC NC NC X E X E a Ordering Code: See Section 6 NC NC NC Pin Assignment for LCC Pin Assignment for DIP, Flatpak and SOIC DC Characteristics unless otherwise specified

AC20

Contextual Info: AC20 54AC/74AC20 Dual 4-Input NAND Gate Connection Diagrams Outputs Source/Sink 24 mA NC NC s rs s Ordering Code: See Section 6 • yi liJ G N D [lb ] r | 2 ' NC N C [11| K . .1 « IX IÏ3 *J- t I20] V c c -ft w jf ¿5] ¡Tèj [if NC NC |i§ NC Pin Assignment