74ALS10 Search Results

74AS1034

Abstract: LS1034
Contextual Info: TYPES SN54ALS1034, SN54AS1034, 74ALS1034, SN74AS1034 HEX DRIVERS D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D D E C E M B E R 1 9 8 3 'A S 1 0 3 4 O ffers High Capacitlve-Drive Capability SN 54ALS1034. S N 54A S1034 . . . J PACKAGE SN 74ALS1034, S N 74A S1034 . . . N PACKAGE

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1035P TËJ MITSUB ISH I {DGTL LOGIC} Q012732 G | HEX NONINVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT / DESCRIPTION PIN CONFIGURATION TOP VIEW ” T h e M 7 4 A L S 1 0 3 5 P is a s e m ic o n d u c to r in te g ra te d c ir­ c u it c o n s is tin g o f six n o n -inverting b u ffe rs w ith open

Contextual Info: Philips Sem iconductors Product specification 7A. Q1flQ. Dual J-K positive edge triggered flip-flop with set and reset PIN CONFIGURATION DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and

Philips Semiconductors Selection Guide

Abstract: 74ALS08
Contextual Info: Philips Semiconductors Functional selection guide GATES FUNCTION INVERTERS NAND NOR DEVICE NUMBER NUMBER OF PINS Hex inverters 74ALS04B 14 Quad 2-input 74ALS00A 14 Triple 3-input 74ALS10A 14 Dual 4-input 74ALS20A 14 8-input 74ALS30A 14 Quint 2-input NAND, open collector

54ALS10A

Abstract: SN54ALS10A SN54AS10 SN74ALS10A SN74AS10
Contextual Info: 74ALS10A, SN74AS10, SN54ALS10A, SN54AS10 TRIPLE 3-INPUT POSITfVE-NAND GATES M A R C H 1 9 8 4 - R E V I S E D M A Y 1986 • • S N 54ALS10A, SN 54AS10 S N 74ALS10A, SN 74AS10 . . Package O p tio n s In clud e P lastic "S m a ll O u tlin e " Packages, C era m ic C hip C arriers,

L1146

Abstract: 74ALS1004
Contextual Info: MITSUBISHI ALSTTLs M 74ALS1004P MITSUBI SHI ÍDGTL LOGIC} TI d e J a a ia ? ib i | ~ HEX IN V E R TIN G DR IVER 7^ y j ' / r DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74ALS1004P is a sem iconductor integrated cir­ cuit consistning of six buffers with inverted outputs.

Contextual Info: SN54ALS1002A, SN 74ALS1002A QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS D2661, DECEMBER 1983-REV lSED MAY 1986 SN54ALS1002A . . . J PACKAGE SN74ALS1Û02A . . . D OR N PACKAGE • Quad Versions of 'A L S 8 0 5 A • Buffer Version of 'A L S 0 2 • Package Options Include Plastic "S m a ll

1u9a

Contextual Info: Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset DESCRIPTION PIN CONFIGURATION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and

Contextual Info: Philips Sem iconductors Product specification Triple 3-input NAND gate TYPE 74ALS10A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 4.0ns 1,8mA PIN CONFIGURATION 1A [T 74ALS10A K J "S| vcc 1B [T ORDERING INFORMATION O RDER CODE CO M M E R C IA L RANGE

F199

Abstract: 74ALS 74ALS10A 74ALS10AD 74ALS10AN
Contextual Info: INTEGRATED CIRCUITS 74ALS10A Triple 3-Input NAND gate Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification Triple 3-input NAND gate TYPE 74ALS10A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT

3rw 44

Abstract: 74ALS109A 74ALS109AD 74ALS109AN SM15C
Contextual Info: 7 4 A L S 109 A . FLIP-FLOP 74ALS109A Dual J-K>osltive Edge-Triggered Flip-Flops With Set and Reset Product Specification DESCRIPTION The 'ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, R, Clock, Set and Reset inputs; also true and complemen­

74ALS

Abstract: 74ALS109A 74ALS109AD 74ALS109AN SC00042
Contextual Info: INTEGRATED CIRCUITS 74ALS109A Dual J-K positive edge-triggered flip-flop with set and reset Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop

TEXTOOL zif 40 pin socket

Abstract: MS-012-AB 74ALS 74ALS109A 74ALS109AD 74ALS109AN SOL-24
Contextual Info: 74ALS109A Signetics FLIP-FLOP 74ALS109A Dual J-K Positive Edge-Triggered Flip-Flops With Set and Reset ALS Products Product Specification DESCRIPTION TYPE The 'ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also true and complemen­

MS-012-AB

Abstract: 74ALS 74ALS10A 74ALS10AD 74ALS10AN SOL-24
Contextual Info: Signetics 74ALS10A Triple 3-Input NAND Gates Product Specification ALS Products FUNCTION TABLE OUTPUT IN P U T S TYPICAL PROPAGATION DELAY TYPE A B C H H H L L X X H X L X H X X L H 7 4A L S 1 0 A 4 .0 ns TYPICAL SUPPLY CURRENT TOTAL 1.0 mA Ÿ NOTES: H = High voltage level

ALS08

Abstract: 54ALS1008 DM74ALS DM74ALS1008AM DM74ALS1008AN J14A M14A N14A
Contextual Info: DM54ALS1008A/DM 74ALS1008A Quadruple 2-Input AND Buffers General Description Features These devices contain four independent 2-input buffers, each of which performs the logic AND function. The ’ALS1008A is a buffer version of the 'ALS08. • Switching specifications at 50 pF

Contextual Info: Philips Semiconductors Product specification Triple 3-input NAND gate TYPE 74ALS10A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 4.0ns 1.8mA 74ALS10A PIN CONFIGURATION ORDERING INFORMATION ORDER CODE DRAWING NUMBER DESCRIPTION COMMERCIAL RANGE

74als1010

Abstract: 74ALS1010A 54als1010
Contextual Info: TYPES SN54ALS1010A, 74ALS1010A TRIPLE 3-INPUT POSITIVE-NAND BUFFERS 0 2 6 6 1 , A P R IL 1 9 8 2 — R E V IS E D D E C E M B E R 1 9 8 3 Buffer Version o f 'A L S 1 0 SN 54 A LS 1 0 1 0 A . . . J PACKAGE Package O ptions Include Both Plastic and Ceram ic C h ip Carriers in Addition to Plastic

LP319

Abstract: IC 74LS00
Contextual Info: I IP 11Q IP7Q 11 LOW POW ER QUAD D IFFER EN TIA L C OM PARATORS 030 44 , OCTOBER 1987-REVISED MAY 1988 • Ultralow Power Supply Current Drain . . . Typically 6 0 /»A • Low Input Biasing Current . . . 3 nA D, J, OR N PACKAGE (TOP VIEW • Low Input Offset Current . . . ± 0 .5 nA

74ALS1011

Abstract: 74ALS1011AM
Contextual Info: TYPES SN54ALS1011A, 74ALS1011A TRIPLE 3 INPUT POSITIVE-AND BUFFERS D 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E O D E C E M B E R 1 9 8 3 • • Buffer Version of 'A L S 1 1 S N 5 4 A L S 1 0 1 1 A . w. J P A C K A G E S N 7 4 A L S 1 0 1 1 A . . . N PACKAG E

74als1035

Contextual Info: TYPES SN54ALS1035, 74ALS1035 HEX NONINVERTING BUFFERS WITH OPEN COLLECTOR OUTPUTS D 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D D E C E M B E R 1 9 8 3 • Noninverting Buffers with Open-Collector Outputs • Package Options Include Both Plastic and Ceram ic

74ALS1000

Abstract: SN54ALS1000A
Contextual Info: TYPES SN54ALS1000A. SN54AS1000, 74ALS1000A, SN74AS1000 QUADRUPLE 2-INPUT POSITIVE NANO BUFFERS/DRIVERS 0 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D D E C E M B E R 1 9 8 3 ' A L S 1 0 0 0 A is a B u ffe r V e r s io n o f SN 54ALS1O O O A, S N 5 4 A S 1 0 0 0 . . . J PA C K A G E

Contextual Info: TOSHIBA TC74VHC1OF/FN/FS/FT TO SHIBA CM OS D IG ITAL INTEGRATED CIRCUIT SILICON M ONOLITHIC TC74VHC10F, TC74VHC10FN, TC74VHC10FS, TC74VHC10FT TRIPLE 3 -INPUT NAND GATE The TC74VHC10 is an advanced high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate C2MOS technology.

TC74VHC10F

Abstract: TC74VHC10FT TC74VHC10 1142A
Contextual Info: TC74VHC10F/FT 東芝CMOSデジタル集積回路 シリコン モノリシック TC74VHC10F,TC74VHC10FT Triple 3-Input NAND Gate TC74VHC10 はシリコンゲート CMOS 技術を用いた超高速 CMOS 3 入力 NAND ゲートです。CMOS の特長である低い消費電

pin diagram of 74ls00

Abstract: TTL 74ls00 LP239J LM239 LM2901 LM339 LP239 LP239D LP2901 LP339
Contextual Info: LP239, LP339, LP2901 LOW-POWER QUAD DIFFERENTIAL COMPARATORS SLCS004A – D3044, OCTOBER 1987 – REVISED MAY 1988 • • • • • • • • • • Ultralow Power Supply Current Drain . . . 60 µA Typ Low Input Biasing Current . . . 3 nA Low Input Offset Current . . . ±0.5 nA