74AS1 Search Results

74AS131

Abstract: H 349
Contextual Info: DM54AS131/74AS131 National JutSemiconductor 74AS131 3-to-8 Line Decoders/Demultiplexers with Address Registers General Description Features The DM54/74AS131 is a 3-to-8 line decoder/dem ultiplexer with registers on the three address inputs. When the clock

Contextual Info: SN54ALS168B, SN54ALS169B, SN54AS168, SN54AS169 S N 74 A LS 16 8 B , S N 74 A LS 16 9 B , S N 74 A S 16 8 , S N 74AS16 9 SYNCHRONOUS 4-BIT UP/DOWN DECADE A N D BINARY COUNTERS M AR C H 1 9 8 4 - • • I Fully Synchronous Operation for Counting and Programming

16-LIN

Contextual Info: a >i MITSUBISHI ASTTLs M 74AS13SP 3-LINE TO 8-LINE DECODER/DEMULTIPLEX ER DESCRIPTION T h e M 7 4 A S 1 3 8 P is a s e m ic o n d u c to r in te g ra te d c irc u it of a 3 - lin e - to - 8 - lin e d e c o d e r /d e m u ltip le x e r w ith PIN CONFIGURATION TOP VIEW

Contextual Info: MITSUBISHI - - - Í D G T iT L O G I C } "il D È I ^24^027 DG12S71 □ ¥ MI T S UB I S H I — ASTTLs M 74AS1808P 91D 12 271 t ò ^ pa's<re 7~ ~93-/S D HEX 2-1NPUT AND DRIVER DESCRIPTION The 74AS1808P is a semiconductor integrated circuit consisting of six 2-input positive-logic AND buffer gates,

Contextual Info: MITSUB IS HI -CD6TL LOGIC} Il 91D D È I bSMTflS? ODlBEhñ □ 12 2 6 8 D >00^ ?^ u MITSUBISHI ASTTLs M 74AS1804P ~ 7^Y3'/S HEX 2-IN PU T NAND DRIVER DESCRIPTION The 74AS1804P is a semiconductor integrated circuit consisting of six 2-input positive-logic NAND buffer

SN54AS182

Abstract: AS181B 13hcn SAN.M06.NLC.5NZ
Contextual Info: C PRODUCT PREVIEW t V -3 SN 54AS182, SN 74AS182 LOOK AHEAD CARRY GENERATOR D 2 6 6 1 , D E C E M B E R 1 9 8 3 - R E V IS E D M A Y 1 9 8 6 • H ig h -S p e e d R e p la c e m e n t f o r th e 'S 1 8 2 • O ffe rs C a rry F u n c tio n s in a C o m p a tib le

Contextual Info: I • M I T S U B I S H I -CDGTL L O GI C} Tl 6 2 4 9 8 2 7 M I T S U B I S H I <DGTL L O G I C 910 12198 ° D eT | b E 4 ciñ57 'DD12nfl S | ~ MITSUBISHI A S T T Ls M 74AS158P r % £ * « * * * T-6.6-21-5-1 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER INVERTED)

74AS13

Abstract: ls 138 74AS138 LS138 SN54ALS138
Contextual Info: SN74ALS138, SN 74AS13«, SN54ALS138, SN54AS138 3-LINE TO B-LINE DECODERS/DEMULTIPLEXERS 02661, APRIL 1982 - REVISED MAY 1986 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems S N 5 4A LS 138, S N 6 4A S 1 38 . . J PACKAGE S N 74A LS 138, S N 7 4A S 1 38

54ALS10A

Abstract: SN54ALS10A SN54AS10 SN74ALS10A SN74AS10
Contextual Info: SN74ALS10A, 74AS10, SN54ALS10A, SN54AS10 TRIPLE 3-INPUT POSITfVE-NAND GATES M A R C H 1 9 8 4 - R E V I S E D M A Y 1986 • • S N 54ALS10A, SN 54AS10 S N 74ALS10A, SN 74AS10 . . Package O p tio n s In clud e P lastic "S m a ll O u tlin e " Packages, C era m ic C hip C arriers,

Contextual Info: MITSUBISHI ASTTLs M 74AS1008AP QUADRUPLE 2-INPUT POSITIVE AND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M 7 4A S 1 008 A P is a sem iconductor integrated circuit consisting of four 2-input positive-logic AND buffer gates, usable as n e g ative-log ic OR buffer gates.

74AS1804

Contextual Info: MITSUBISHI ASTTLs -*00°° M 74AS1804P HEX 2-INPUT NAND DRIVER DESCRIPTION The 74AS1804P is a semiconductor integrated circuit consisting of six 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates. PIN CONFIGURATION TOP VIEW

Contextual Info: MITSUBISHI -CDGTL L O G I C ! TI D e J bEM^flaV Q G 1 S 2 7 4 b "|~ MITSUBISHI ASTTLs & « l'" * ' í W 1 M 74AS1832P 1 -T -V 3 -/S s'*"*5*”' HEX 2-INPUT OR DRIVER 6249827 MITSUBISHI <DG T L LOGI C DESCRIPTION T h e M 7 4 A S 1 8 3 2 P is a sem iconductor integrated circuit

74AS194

Abstract: 54AS194
Contextual Info: TYPES SN 54AS194, SN 74AS194 4 BIT BID IRECTIO NAL U N IV ER S A L SH IFT R EG ISTERS D 2 6 6 1 , DECEM BER 1 9 8 3 • Parallel-to-Serial, Serial-to-Parallel Conversions • Left or Right Shifts • Parallel Synchronous Loading • Direct Overriding Clear

74AS138

Contextual Info: PRELIMINARY DM54AS138/74AS138 3-to-8 Line Decoder/ Demultiplexer General Description Features The DM54/74AS138 c ircuit is designed to be used in high perform ance memory decoding or data routing applica­ tions requiring very short propagation delay times. In high

Contextual Info: MITSUBISHI ASTTLs M 74AS1034AP .MV"4 HEX DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M 7 4A S 1 034 A P is a sem iconductor integrated circuit consisting of six non-inverting drivers. FEATURES IN P U T • High fan-out ( l 0 L= 48mA, Io h ^ - 48m A )

74AS1008A

Contextual Info: NATIONAL SEniCOND { L O G I C } hl DE| b S G U S S DGSlflbb 7 6501122 NATIONAL SEMICONDUCTOR 6 1 C 51866 D T-43-1S D M 54AS1008A/ D M 74AS1008A Quadruple 2-Input AND Drivers General Description Absolute Maximum Ratings Notei These devices contain four independent 2-input drivers,

74AS1000

Contextual Info: MITSUBISHI A STTLs M 74AS1000AP QUADRUPLE 2-INPUT POSITIVE NAND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The 74AS1000AP is a semiconductor integrated circuit consisting of four 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates.

54ALS151

Abstract: 54AS151
Contextual Info: TYPES SN54ALS151, SN54AS151, SN74ALS151, 74AS151 1 OF 8 DATA SELECTORS/MULTIPLEXERS D 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D D E C E M B E R 1 9 8 3 8-Line to 1-Line Multiplexers Can Perform As: Boolean Function Generators Parallel-to-Serial Converters

Contextual Info: TEXAS INSTR 0=^1723 oaaBü? 1 5SE D LOGIC SN54ALS131, SNB4AS131A, SN74ALS131, 74AS131A 3-LINE TO 8-LINE DECODERSIDEMULTIPLEXERS WITH ADDRESS REGISTERS r-<U.-2('55 D 2 6 6 1 , A PRIL 1 9 8 2 - R E V IS E D M AY 1986 SN54ALS131, SN54AS131A . . . J PACKAGE

TMX320VC33

Abstract: SPRS087E tms320vc33pgea120 TMS320C31 TMS320VC33 TMS320VC33-120 TMS320VC33-150 vc33 jtag tms320 lot trace DUPONT CONNECTOR
Contextual Info: TMS320VC33 DIGITAL SIGNAL PROCESSOR SPRS087E - FEBRUARY 1999 - REVISED JANUARY 2004 D High-Performance Floating-Point Digital D D D D D D D D D D Signal Processor DSP : - TMS320VC33-150 - 13-ns Instruction Cycle Time - 150 Million Floating-Point Operations

SPDU079A

Abstract: ACT8990 XDS510 MPSD 74AS1004 JTAG(MINI)14 pin 74F175 74LVT240 ACT8999 TL7705A XDS510
Contextual Info: JTAG/MPSD Emulation Technical Reference 1994 Printed in U.S.A., December 1994 2617709–9741 revision A SPDU079A JTAG/MPSD Emulation Technical Reference December 1994 SPDU079 Printed on Recycled Paper Running Title—Attribute Reference IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any

SM320VC33

Contextual Info: SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 D High-Performance Floating-Point Digital D Signal Processor DSP : - SM/SMJ320VC33-150 - 13-ns Instruction Cycle Time - 150 Million Floating-Point Operations Per Second (MFLOPS)

SN54ALS11A

Abstract: SN54AS11 SN74ALS11A SN74ALS11AD SN74ALS11ADR SN74ALS11AN SN74AS11 SN74AS11D SN74AS11N
Contextual Info: SN54ALS11A, SN54AS11, SN74ALS11A, 74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009D – MARCH 1984 – REVISED NOVEMBER 2002 4.5-V to 5.5-V VCC Operation Max tpd of 5.5 ns at 5 V SN54ALS11A, . . . J OR W PACKAGE SN54AS11 . . . J PACKAGE SN74ALS11A, 74AS11 . . . D, N, OR NS PACKAGE

ALS174

Abstract: SN54ALS174 SN54ALS175 SN54AS174 SN54AS175B SN74ALS174 SN74ALS175 SN74AS174 SN74AS175B
Contextual Info: SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, 74AS174, 74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDAS207E - APRIL 1982 - REVISED MAY 2002 D D D ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs ’ALS175 and ’AS175B Contain Four