74AS138 Search Results

74AS138

Contextual Info: PRELIMINARY DM54AS138/74AS138 3-to-8 Line Decoder/ Demultiplexer General Description Features The DM54/74AS138 c ircuit is designed to be used in high perform ance memory decoding or data routing applica­ tions requiring very short propagation delay times. In high

74LS90

Abstract: AM6012 LT1022 LTC1099 LTC1099A LTC1099ACN LTC1099AIN LTC1099CN 20pin 4bit adc
Contextual Info: LTC1099 High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold DESCRIPTIO U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC 1099 is a high speed microprocessor compatible 8-bit analog-to-digital converter A/D . An internal sampleand-hold (S/H) allows the A/D to convert inputs up to the

application of 74LS90

Abstract: 74as00
Contextual Info: LTC1099 High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold DESCRIPTIO U FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC 1099 is a high speed microprocessor compatible 8-bit analog-to-digital converter A/D . An internal sampleand-hold (S/H) allows the A/D to convert inputs up to the

74LS244 diagram

Abstract: 74LS31 74LS373 Decoder pin BYU29 TMS32010 74ALS02 74ALS32 ADC80Z 74F245 74LS373
Contextual Info: Chapter 5 Theory of Operation The AIB has three basic input/output I/O ports: an analog I/O port, an expansion I/O port, and an extended memory interface port. The analog input port consists of an anti-aliasing filter, a sample and hold circuit, and an analog-to-digital (A/D) converter. The analog output port consists of a digital-toanalog converter, a smoothing filter, an an optional audio output amplifier. The expansion input port provides sixteen buffered inputs, and the expansion output port

DSP stereo based on tms320

Abstract: SPRU031D DSP101 class d Sinus inverter circuit diagram schematics TMS320C30 TMS320C30-40 TMS320C31 TMS320C31-40 TMS320C31-50 TMS320C31PQA
Contextual Info: TMS320C3x User’s Guide 2558539-9721 revision J October 1994 TMS320C3x User’s Guide 1994 Digital Signal Processing Products Printed in U.S.A., October 1994 2558539-9761 revision J SPRU031D User’s Guide TMS320C3x 1994 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any

Architecture of TMS320C28

Abstract: fetal monitor device circuit diagrams texas instrument 74HC14 TMS320 TMS32010 TMS320C10 TMS320C25 TMS320C25-50 TMS320C26 TMS320C28
Contextual Info: TMS320C2x User's Guide 1604907-9761 revision C January 1993 Running Title—Attribute Reference Chapter 1 Introduction The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed controller with the numerical capability of an array

74AS13

Abstract: ls 138 74AS138 LS138 SN54ALS138
Contextual Info: SN74ALS138, SN 74AS13«, SN54ALS138, SN54AS138 3-LINE TO B-LINE DECODERS/DEMULTIPLEXERS 02661, APRIL 1982 - REVISED MAY 1986 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems S N 5 4A LS 138, S N 6 4A S 1 38 . . J PACKAGE S N 74A LS 138, S N 7 4A S 1 38

Contextual Info: LTC1099 High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold DESCRIPTIO FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ U ■ The LTC 1099 is a high speed microprocessor compatible 8-bit analog-to-digital converter A/D . An internal sampleand-hold (S/H) allows the A/D to convert inputs up to the

9737

Abstract: 74AS32 74AS373 AN-543 C1995 DP8420A DP8422A PAL16R6B
Contextual Info: I INTRODUCTION This application note describes how to interface the National Semiconductor NS32332 microprocessor to the DP8422A DRAM controller also applicable to DP8420A 21A There are four designs shown in this application note The differences between these designs are as

74AS139

Abstract: block diagram of 80386 microprocessor 82384 80386 microprocessor block diagram 80386 microprocessor features 80386 microprocessor 74as175 cpu 80386 80386 82384 clock
Contextual Info: INTRODUCTION This application note describes how to interface the 80386 microprocessor to the DP8422A DRAM controller also applicable to DP8420A 21A The 80386 is interfaced with the DP8422A in both address pipelined (Design 1) and nonaddress pipelined (Design 2) mode up to 50 MHz (8038625) It is assumed that the reader is already familiar with

DP8422-25

Abstract: PAL16L8 programming specifications 74AS374 74F245 AN-602 C1995 DP8420A DP8422A PAL16L8D 74F245 national
Contextual Info: INTRODUCTION This application note describes how to interface the 29000 microprocessor to the DP8422A DRAM controller also applicable to DP8420A 21A The DP8422A supports the 29000 in the burst access mode It is assumed that the reader is already familiar with 29000 access cycles and the

74AS138

Abstract: 54AS138 LS138 SN54ALS138
Contextual Info: SN54ALS138, SN54AS138, SN74ALSI38, 74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D 2 6 6 1 , A P R IL 1 9 8 2 - R E V l S E D M A Y 1 9 8 6 • • • • Designed Specifically for High-Speed M em ory Decoders and Data Transmission Systems SN 5 4 A LS1 3 8 , SN 54A S 138 . . . J PACKAG E

SN54ALS138

Contextual Info: SN74ALS138, 74AS138, SN54ALS138, SN54AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D2661, APRIL 1982 - REVISED MAY 1986 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN54ALS138, SN54AS138 . J PACKAGE SN74ALS138, SN74AS136

Contextual Info: M ITSUBISHI íDGTL LOGIC} TI 6249827 M ITS U B IS H I D E | bSM'lflS? ODISIIS 4 ÍDGTL L O Q IC 91D 12192 D MITSUBISHI ASTTLs A m -9 J t A ^ IYI M T-66-21-55 tío'"'*’ nata'"- I 5°^9_3-LINE TO 8-LIN E DECODER/PEMULTIPLEXER

74aLS808

Abstract: 74ALS677 74ALS468 SN74AS877 SN74LS630 SM54A NCE 7190 74ls631 SN74LS693 TTL Data Book for Design Engineers
Contextual Info: ADVANCED LOW-POWER SCHOTTKY AND ADVANCED SCHOTTKY CIRCUITS FUNCTION DEVICE AS1032 ALS1034 AS1034 Quad 2-Input OR Buffers/ Drivers A VAILABILITY NOW NOW NOW Hex Drivers NOW ALS1035 Hex Buffers with D-C Outputs NOW AS1036 Quad 2-Input NOR Line Driver NOW ALS1240

74as04

Abstract: 74AS138 74as74 74as02 68450 TL E28 74AS245 AN-538 C1995 DP8420A
Contextual Info: National Semiconductor Application Note 538 Joe Tate and Rusty Meier May 1989 INTRODUCTION This application note explains interfacing the DP8420A 21A 22A DRAM controller to the 68000 Three different designs are shown and explained It is assumed that the reader is familiar with the 68000 access cycles and

SN54ALS138

Contextual Info: SN54ALS138A, SN54AS138, SN74ALS138A, 74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDAS055E – APRIL 1982 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify

RF transmitter and Receiver circuit for robot con

Abstract: TMS320C26BFN TMP38 TMS3477 TCM5094 TMS4461 TMS320C2x architecture cell phone CONTROLLED ROBOT tms2764 ti databook 1974
Contextual Info: TMS320C2x User's Guide 1604907-9761 revision C January 1993 Running Title—Attribute Reference Chapter 1 Introduction The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed controller with the numerical capability of an array

TMS3477

Abstract: voice control robot circuits diagram block diagram of 74LS138 3 to 8 decoder ti databook 1974 texas databook 1974 texas instrument 74HC14 LTA 702 N 74als04a 74ALS138 CI 74S04
Contextual Info: TMS320C2x User's Guide SPRU014C October 1992 Running Title—Attribute Reference Chapter 1 Introduction The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed controller with the numerical capability of an array

74AS245

Abstract: 74AS04 DP8422 68020 74AS74 SA-47B 68020 74AS32 AN-539 C1995 DP8420A
Contextual Info: National Semiconductor Application Note 539 Joe Tate and Rusty Meier May 1989 INTRODUCTION This application note explains interfacing the DP8420A 21A 22A DRAM controller to the 68020 microprocessor Three different designs are shown and explained It is assumed that the reader is already familiar with

74AS244

Abstract: 100541 74AS32 AN-541 C1995 DP8420A DP8422A NS32532 PAL16R4D 32NS-2A
Contextual Info: 1 0 INTRODUCTION This application note describes how to interface the National Semiconductor NS32532 microprocessor to the DP8422A DRAM controller also applicable to DP8420A 21A It is assumed that the reader is already familiar with NS32532 and the DP8422A modes of operation

TMS7000 instruction set

Abstract: TMS77C82 D780C-1 TMS7000 assembler guide TMS70C00 TMS7000 TMS7000NL-2 TMS7000 Family Data Manual 77C82 TMS70C02N
Contextual Info: TMS7000 Family Data Manual 8-bit Microcomputer Family * Te x a s In s t r u m e n t s IM PO R TAN T NOTICE Texas Instruments Tl reserves the right to make changes in the devices or the device specifications identified in this publication without notice. Tl advises

SN54ALS138

Contextual Info: SN54ALS138A, SN54AS138, SN74ALS138A, 74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDAS055E – APRIL 1982 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify

equivalent for C3150

Abstract: tartan 74ALS138 TMS320C25 echo SPRU031D TSP53C30 DSP101 tms320c3x boot loader AD1678 BEL 1895
Contextual Info: TMS320C3x User’s Guide 2558539-9721 revision J October 1994 TMS320C3x User’s Guide 1994 Digital Signal Processing Products Printed in U.S.A., October 1994 2558539-9761 revision J SPRU031D User’s Guide TMS320C3x 1994 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any