74AUP2G240GM Search Results

74AUP2G240GM Datasheets (4)

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
74AUP2G240GM		NXP Semiconductors	Low-power dual inverting buffer/line driver; 3-state	Original	PDF	100.85KB	20
74AUP2G240GM		NXP Semiconductors	74AUP2G240 - IC AUP/ULP/V SERIES, DUAL 1-BIT DRIVER, INVERTED OUTPUT, PBCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT902-1, QFN-8, Bus Driver/Transceiver	Original	PDF	304.48KB	25
74AUP2G240GM,125		NXP Semiconductors	Low-power dual inverting buffer/line driver; 3-state; Package: SOT902-1 (XQFN8U); Container: Reel Pack, Reverse, Reverse	Original	PDF	100.85KB	20
74AUP2G240GM,125		NXP Semiconductors	74AUP2G240 - IC AUP/ULP/V SERIES, DUAL 1-BIT DRIVER, INVERTED OUTPUT, PQCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT-902-1, XQFN-8, Bus Driver/Transceiver	Original	PDF	304.48KB	25

74AUP2G240GM Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
74AUP2G240 Abstract: 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78 Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 03 — 7 April 2009 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE	Original	74AUP2G240 74AUP2G240 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78	PDF
74AUP2G240 Abstract: 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78 Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 04 — 30 June 2009 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE	Original	74AUP2G240 74AUP2G240 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78	PDF
Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 01 — 6 October 2006 Product data sheet 1. General description The 74AUP2G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.	Original	74AUP2G240 74AUP2G240 The18	PDF
74AUP2G240 Abstract: 74AUP2G240DC 74AUP2G240GT JESD78 Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 5 — 13 September 2010 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE	Original	74AUP2G240 74AUP2G240 74AUP2G240DC 74AUP2G240GT JESD78	PDF
Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 8 — 24 January 2013 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE	Original	74AUP2G240 74AUP2G240	PDF
Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 7 — 6 June 2012 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE	Original	74AUP2G240 74AUP2G240	PDF
Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 6 — 5 December 2011 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE	Original	74AUP2G240 74AUP2G240	PDF
74AUP2G240 Abstract: 74AUP2G240DC 74AUP2G240GM 74AUP2G240GT JESD22-A114D JESD78 Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 02 — 22 February 2008 Product data sheet 1. General description The 74AUP2G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS-compatible TTL families.	Original	74AUP2G240 74AUP2G240 74AUP2G240DC 74AUP2G240GM 74AUP2G240GT JESD22-A114D JESD78	PDF
NC7WZ240K8X Abstract: 74AUP2G240 74LVC2G240 NC7WZ240 SN74AUC2G240 SN74AUP2G240 SN74LVC2G240 Silego Technology dual inverting schmitt-trigger Contextual Info: SLG74LB2G240 GreenLIBTM DUAL INVERTING BUFFER/DRIVER WITH TRI-STATE OUTPUTS General Description Features The GreenLIB provides the dual inverting buffer/driver with • Pb-Free / RoHS Compliant tri-state outputs. The tri-state outputs are controlled by •	Original	SLG74LB2G240 000-0074LB2G240-11 NC7WZ240K8X 74AUP2G240 74LVC2G240 NC7WZ240 SN74AUC2G240 SN74AUP2G240 SN74LVC2G240 Silego Technology dual inverting schmitt-trigger	PDF
Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 7 — 6 June 2012 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE	Original	74AUP2G240 74AUP2G240	PDF