74AUP2G79GT Search Results
74AUP2G79GT Datasheets (5)
Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
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74AUP2G79GT |
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Low-power dual D-type flip-flop, positive-edge trigger | Original | 92.41KB | 19 | ||
74AUP2G79GT |
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Low-power dual D-type flip-flop; positive-edge trigger | Original | 99.01KB | 21 | ||
74AUP2G79GT |
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74AUP2G79 - IC AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, SON-8, FF/Latch | Original | 301.99KB | 25 | ||
74AUP2G79GT,115 |
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Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT833-1 (XSON8U); Container: Reel Pack, SMD, 7" | Original | 99.01KB | 21 | ||
74AUP2G79GT,115 |
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74AUP2G79 - IC AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-833-1, SON-8, FF/Latch | Original | 301.99KB | 25 |
74AUP2G79GT Price and Stock
Nexperia 74AUP2G79GT,115IC FF D-TYPE DOUBLE 1-BIT 8XSON |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74AUP2G79GT,115 | Cut Tape | 1 |
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74AUP2G79GT,115 | Reel | 6 Weeks | 5,000 |
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74AUP2G79GT,115 |
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74AUP2G79GT,115 | Cut Tape | 1 |
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74AUP2G79GT,115 | Reel | 5,000 |
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74AUP2G79GT,115 | 8 Weeks | 5,000 |
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74AUP2G79GT,115 | 5,000 | 8 Weeks | 5,000 |
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NXP Semiconductors 74AUP2G79GT,11574AUP2G79GT - D Flip-Flop, AUP/ULP/V Series, 2-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO8 |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74AUP2G79GT,115 | 130,247 | 1 |
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74AUP2G79GT Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Dual D-type flip-flop positive-edge triggerContextual Info: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 6 — 8 December 2011 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the |
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74AUP2G79 74AUP2G79 Dual D-type flip-flop positive-edge trigger | |
Dual D-type flip-flop positive-edge trigger
Abstract: JESD22-A114E JESD78 74AUP2G79 74AUP2G79DC 74AUP2G79GT p79 marking
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74AUP2G79 74AUP2G79 Dual D-type flip-flop positive-edge trigger JESD22-A114E JESD78 74AUP2G79DC 74AUP2G79GT p79 marking | |
74AUP2G79
Abstract: 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT JESD22-A114E JESD78
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74AUP2G79 74AUP2G79 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT JESD22-A114E JESD78 | |
Contextual Info: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 8 — 24 January 2013 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the |
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74AUP2G79 74AUP2G79 | |
74AUP2G79
Abstract: 74AUP2G79DC 74AUP2G79GT JESD78
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74AUP2G79 74AUP2G79 74AUP2G79DC 74AUP2G79GT JESD78 | |
74AUP2G79
Abstract: 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT SN74AUC2G79 SN74AUC2G79DCTR
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SLG74LB2G79 LB2G79 000-0074LB2G79-11 74AUP2G79 74AUP2G79DC 74AUP2G79GM 74AUP2G79GT SN74AUC2G79 SN74AUC2G79DCTR | |
Contextual Info: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 01 — 6 October 2006 Product data sheet 1. General description The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. |
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74AUP2G79 74AUP2G79 | |
74AUP2G79
Abstract: 74AUP2G79DC 74AUP2G79GT JESD22-A114E JESD78
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74AUP2G79 74AUP2G79 74AUP2G79DC 74AUP2G79GT JESD22-A114E JESD78 | |
Contextual Info: 74AUP2G79 Low-power dual D-type flip-flop; positive-edge trigger Rev. 7 — 14 June 2012 Product data sheet 1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input nD is transferred to the nQ output on the LOW-to-HIGH transition of the |
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74AUP2G79 74AUP2G79 |