74F10 Search Results

motorola F74

Abstract: 74F109
Contextual Info: The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop refer to F74 data sheet by connecting the J and K inputs together.

dual d flip-flop

Abstract: t flipflop 74F109
Contextual Info: MOTOROLA DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking_operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D

74f740

Abstract: 74F5074D
Contextual Info: Philip* Semlconductora-Signetic* FAST Producto Product »pacification Synchronizing dual J - K positive edge-triggered flip-flop with metastable immune characteristics FEATURE • Pinout compatible with 74F109 • Metastable immune characteristics • Output skew guaranteed less than 1.5ns

Contextual Info: EM IC O N D U C T O R T 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Fast bipolar voltage clam ping action General Description Dual ce nte r pin grounds fo r min inductance The ’F1071 is an 18-bit undershoot/overshoot clam p which

a215c

Abstract: 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
Contextual Info: A p riM 9 8 8 Revised January 1999 74F109^ Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to Cp sets Q to LOW level T he F 1 09 consists of tw o high-speed, com pletely indepen­ dent transition clocked JK flip-flops. The clocking operation

74F10

Contextual Info: M MOTOROLA MC54/74F10 TRIPLE 3-INPUT NAND GATE TR IPLE 3 -IN P U T NAND GATE FAST SCHOTTKY TTL vcc = ir > ) J SUFFIX CERAMIC CASE 632-06 .i 14 1 GND N SUFFIX PLASTIC CASE 646-06 D SUFFIX soie 14 1 CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN MC74FXXD

Contextual Info: 10 54F/74F10 Triple 3-Input NAND Gate Connection Diagrams NC NC 0 B 0 ÎÎ 0 Ordering Code: See S ection 5 Pin Assignment for LCC and PCC Pin Assignment for DIP and SOIC Input Loading/Fan-Out: See S ection 3 fo r U.L. d e fin itio n s 54F/74F U.L. Description

74F109

Abstract: 9471 54F109DM 54F109FM 54F109LM 74F109PC 74F109SC 74F109SJ F109 J16A
Contextual Info: 54F 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed completely independent transition clocked JK flip-flops The clocking operation is independent of rise and fall times of the clock waveform The JK design allows operation as a D flip-flop refer to ’F74

jedec MO-150

Abstract: IEC-801-2 IEC801-2 jedec ms-013 74F1071SC IEC-801-2 ESD 74F1071 74F1071MSA 74F1071MSAX 74F1071MTC
Contextual Info: Revised March 2005 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device General Description Features The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to

74F109

Contextual Info: *p n l1 9 , æ Revised January 1999 SEMICONDUCTOR TM 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to C q sets Q to LOW level The F109 consists of tw o high-speed, com pletely indepen­ den t transition clocked JK flip-flops. The clocking operation

74F109

Abstract: 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
Contextual Info: Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.

150pf 6kv

Abstract: 74F1071MTC 74F1071SC MO-150 MS-013 MSA20 MTC20 74F1071 74F1071MSA
Contextual Info: 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Features General Description • 18-bit array structure in 20-pin package The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress

74F10

Abstract: 74F11 n74f10 N74F10D N74F10N N74F11D N74F11N
Contextual Info: Philips Semiconductors-SigneHcs Document No. 853-0329 ECN No. 97683 Date o f issue September 2 0 ,1 98 9 Status Product Specification FAST 74F10, 74F11 Gates 74F10 Triple 3-Input NAND Gate 74F11 Triple 3-Input AND Gate FAST Products TYPE TYPICAL PROPAGATION

74F1056

Abstract: 74F1056SC C1995 M16A b50 diode
Contextual Info: 74F1056 8-Bit Schottky Barrier Diode Array General Description Features The ’F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines This device is designed to suppress negative transients caused by line reflections switching

8 pin dip j k flipflop ic

Abstract: 74f728 Toggle flip flop IC 74F729 74F109A kO314 74F109 N74F109AD N74F109AN internal diagram of jk flipflop
Contextual Info: FAST 74F109A FLIP-FLOP Synchronizing Dual J-K Positive Edge-Triggered Flip-Flops Preliminary Specification FEATURES • Metastable Immune Characteris­ tics • Same pinout and function as 74F109 • See 74F74A for Synchronizing Dual D-Type Flip-Flop • See 74F728 for Synchronizing

74F109

Abstract: F109 74F109PC 74F109SC 74F109SJ M16A M16D MS-001 N16E 74f109 fairchild
Contextual Info: Revised September 2000 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.

schmitt trigger non inverting

Abstract: 74F864 3 bit magnitude comparator 74F154 74F579 74F5300 equivalent multiplexer 30 pin QUAD D FLIP-FLOP "FAST TTL" 74*545
Contextual Info: Philips Semiconductors Section 2 FAST TTL Logic Devices FAST TTL Logic Series CONTENTS 74F00 74F02 74F04 74F06 74F06A 74F07 74F07A 74F08 74F10 74F11 74F14 74F20 74F27 74F30 74F32 74F37 74F38 74F51 74F64 74F74 74F85 74F86 74F109 74F112 74F113 74F125 74F126

IEC-801-2 ESD

Abstract: 74F1071 74F1071MSA 74F1071MTC 74F1071SC MSA20 MTC20
Contextual Info: 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device General Description The ’F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge ESD . The inputs of the device aggressively

Contextual Info: o o> National Semiconductor 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: LOW input to S d sets Q to HIGH level LOW input to C q sets Q to LOW level Clear and Set are independent of clock _ Simultaneous LOW on C q and S q makes both Q and Q

74F1050

Abstract: 9.D8
Contextual Info: ADVANCE INFORMATION Semiconductor 1050 ß National 74F1050 12-Bit Schottky Barrier Diode Array General Description Features The ’F1050 is a 12-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress

74F10

Contextual Info: Signetics FAST 74F10, 74F11 Gates 74F10 Triple 3-Input NAND Gate 74F11 Triple 3-Input AND Gate FAST Products Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT T O T A L 74F10 3.5ns 3.3mA 74F11 4.2ns 5.3mA ORDERING INFORMATION COMMERCIAL RANGE

Contextual Info: National Semiconductor 54F/74F10 Triple 3-Input NAND Gate Ordering Code: see section5 Connection Diagrams Logic Symbol Pin A ssignm ent fo r DIP, SOIC and Flatpak IE E E /IE C *0 - Pin A ssignm ent fo r LCC and PCC C, NC B, NC A, , W 14 2 E l E B m GD

74F109

Contextual Info: Signetics 74F109 FLIP-FLOP Dual J-K Positive Edge-Triggered Flip-Flops FAST Products DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also true and complementary outputs. Set S . and Reset (R ) are asynchronous

751A-02

Abstract: 74F10 74f10 motorola
Contextual Info: MC54/74F10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE FAST SCHOTTKY TTL VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 7 14 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC54FXXJ MC74FXXN