74H10 Search Results

74H10 Result Highlights (2)

Part	ECAD Model	Manufacturer	Description	Download	Buy
74H101PC		Rochester Electronics LLC	74H101 - AND-OR Gated J-K Negative EDGE Triggered FlipFlop
74H106PC		Rochester Electronics LLC	74H106 - J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP16

74H10 Price and Stock

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Rochester Electronics LLC 74H10DC IC GATE NAND 3CH 3-INP 14CERDIP
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DigiKey	74H10DC	Bulk			155	1 - 10 - 100 - 1000 $1.94 10000 $1.94	Buy Now
Rochester Electronics LLC 74H101PC 74H101PC
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DigiKey	74H101PC	Bulk			6	1 - 10 $53.11 100 $53.11 1000 $53.11 10000 $53.11	Buy Now
Rochester Electronics	74H101PC		1,684		1	1 $51.07 10 $51.07 100 $48.01 1000 $43.41 10000 $43.41	Buy Now
Rochester Electronics LLC SN74H102N J-K FLIP-FLOP
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DigiKey	SN74H102N	Bulk			105	1 - 10 - 100 - 1000 $2.88 10000 $2.88	Buy Now
Cynergy3 Components LLF74H100RN SENSOR LEVEL SWITCH SINGLE FLOAT
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DigiKey	LLF74H100RN	Bag			5	1 - 10 $41.6 100 $41.6 1000 $41.6 10000 $41.6	Buy Now
Newark	LLF74H100RN	Bulk			5	1 $43.7 10 $42.61 100 $39.32 1000 $39.32 10000 $39.32	Buy Now
RS	LLF74H100RN	Bulk		8 Weeks	5	1 - 10 $42.02 100 $37.81 1000 $37.81 10000 $37.81	Get Quote
Sager	LLF74H100RN				1	1 $41.6 10 $39.61 100 $36.7 1000 $36.7 10000 $36.7	Buy Now
Cynergy3 Components TSF74H100DN SENSOR LEVEL SWITCH SINGLE FLOAT
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DigiKey	TSF74H100DN	Bulk			1	1 $42.86 10 $42.86 100 $42.86 1000 $42.86 10000 $42.86	Buy Now
Newark	TSF74H100DN	Bulk			1	1 $44.57 10 $42.45 100 $40.52 1000 $40.52 10000 $40.52	Buy Now
RS	TSF74H100DN	Bulk		8 Weeks	1	1 $42.86 10 $40.82 100 $38.96 1000 $38.96 10000 $38.96	Get Quote
Sager	TSF74H100DN				1	1 $42.86 10 $40.82 100 $37.82 1000 $37.82 10000 $37.82	Buy Now

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74H10 Datasheets (31)

Part	Manufacturer	Description	Datasheet Type	PDF
74H10	Fairchild Semiconductor	Full Line Condensed Catalogue 1977	Scan	PDF
74H10	Unknown	TTL Data Book 1980	Scan	PDF
74H10	Signetics	Integrated Circuits Catalogue 1978/79	Scan	PDF
74H101	Fairchild Semiconductor	Full Line Condensed Catalogue 1977	Scan	PDF
74H101	Signetics	Integrated Circuits Catalogue 1978/79	Scan	PDF
74H101DC	Fairchild Semiconductor	JK Edge Triggered Flip-Flop	Scan	PDF
74H101FC	Fairchild Semiconductor	JK Edge Triggered Flip-Flop	Scan	PDF
74H101PC	Fairchild Semiconductor	JK Edge Triggered Flip-Flop	Scan	PDF
74H102	Fairchild Semiconductor	Full Line Condensed Catalogue 1977	Scan	PDF
74H102	Signetics	Integrated Circuits Catalogue 1978/79	Scan	PDF
74H102DC	Fairchild Semiconductor	JK Edge Triggered Flip-Flop	Scan	PDF
74H102FC	Fairchild Semiconductor	JK Edge Triggered Flip-Flop	Scan	PDF
74H102PC	Fairchild Semiconductor	JK Edge Triggered Flip-Flop	Scan	PDF
74H103	Fairchild Semiconductor	Full Line Condensed Catalogue 1977	Scan	PDF

74H103	Signetics	Integrated Circuits Catalogue 1978/79	Scan	PDF
74H103DC	Fairchild Semiconductor	Dual JK Edge Triggered Flip-Flop	Scan	PDF
74H103FC	Fairchild Semiconductor	Dual JK Edge Triggered Flip-Flop	Scan	PDF
74H103PC	Fairchild Semiconductor	Dual JK Edge Triggered Flip-Flop	Scan	PDF
74H106	Fairchild Semiconductor	Full Line Condensed Catalogue 1977	Scan	PDF
74H106	Signetics	Integrated Circuits Catalogue 1978/79	Scan	PDF

74H10 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
7472 PIN DIAGRAM Abstract: 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476 Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 A 4 — J. 9— 10 So « Q — 2 J U» CP o 1— CD 0—3 ¿ So Q CP 8_ K Ä Q Co —I I_ Vcc = Pin 14 GND = Pin 7 in Ü Q UJ EDGE-TRIGGERED 9 O (9 D58 54H/74H106 D59b 54H/74H108	OCR Scan	PDF	54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54H/74H73 54H/74H103 54S/74S113 7472 PIN DIAGRAM 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476
NAND Gate 3-Input 7410 Abstract: 74LS10PC Text: 10 CO NNECTIO N DIAGRAMS PINO UT A '''54/7410 ^é4H/74H10 ^54S/74S10 ö / ' o -h? ^ 4 L S /7 4 L S 1 0 ^ / y 7 TRIPLE 3-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE M ILITARY GRADE V cc = +5.0 V ±5%, T a = 0° C to +70° C	OCR Scan	PDF	4H/74H10 54S/74S10 7410PC, 74H10PC 74S10PC, 74LS10PC 7410DC, 74H10DC 74S10DC, 74LS10DC NAND Gate 3-Input 7410
74H106 Abstract: 54H106 ScansUX995 Text: FAIRCHILD HIGH SPEED TTL/SSI . 9H106/54H106, 74H106 DUAL JK EDGE TRIGGERED FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS D E S C R IP T IO N - T h e H S T T L /S S I 9 H 1 0 6 /5 4 H 1 0 6 , 7 4 H 1 0 6 is a H igh Speed J K N eg ative Edge T rig g e re d flip - f lo p . T h e y fe a tu re in d iv id u a l J, K ,	OCR Scan	PDF	9H106/54H106, 74H106 280ft 54H106 ScansUX995
121122 Abstract: 74H101 ScansUX995 Text: FAIRCHILD HIGH SPEED TTL/SSI . 9H101/54H101, 74H101 JK EDGE TRIGGERED FLIP-FLOP WITH AND-OR INPUTS D E S C R IP T IO N — T h e H S T T L /S S I 9 H 1 0 1 /5 4 H 1 0 1 , 7 4 H 1 0 1 is a H igh S peed J K N eg ative Edge T rig g e re d f lip - f lo p . T h e A N D - O R gate in p u ts are	OCR Scan	PDF	9H101/54H101, 74H101 280ft 121122 ScansUX995
CD 76 13 CP Abstract: 54H108DM 54H108FM 74H108DC 74H108FC 74H108PC Text: 108 C O N N E C T IO N DIAGRAM P IN O U T A 54H/74H108 6//^ 7 DUAL JK E D G E -T R IG G E R E D F LIP -F LO P With Separate Sets, A Com m on Clear and Clock K, [7 TTI Vcc ÏT Iso i Qi \|T D ESCRIPTION — T h e ’ 108 is a h ig h sp eed J K n e g a tive e d g e -trig g e re d flip	OCR Scan	PDF	54H/74H108 54/74H CD 76 13 CP 54H108DM 54H108FM 74H108DC 74H108FC 74H108PC
CD 76 13 CP Abstract: No abstract text available Text: 108 CONNECTION DIAGRAM PINOUT A 54H/74H108 6 //t>/7 DUAL JK EDGE-TRIGGERED FLIP-FLOP With Separate Sets, A Common Clear and Clock DESCRIPTION — The '108 is a high speed J K negative edge-triggered flipflop. It features individual J , K, and asynchronous Set inputs to each flip-flop	OCR Scan	PDF	54H/74H108 54/74H CD 76 13 CP
74H103 Abstract: clock schematic ScansUX995 Flip-Flop on off 54H103 Text: FAIRCHILD HIGH SPEED TTL/SSI • 9H103/54H103, 74H103 DUAL JK EDGE TRIGGERED FLIP-FLOP WITH SEPARATE CLEARS AND CLOCKS DESCRIPTION - The HSTTL/SSI 9H 103/54H 103, 74H 103 is a High Speed JK Negative Edge Triggered flip -flo p . They feature individual J, K,	OCR Scan	PDF	9H103/54H103, 74H103 clock schematic ScansUX995 Flip-Flop on off 54H103
74H101 Abstract: No abstract text available Text: n a t i o n a l s e n I c o n d -clogio 0 2 e d I b s o n a B Got377s 3 I T -^ 6 -0 7 '0 7 101 CO N N ECTIO N DIAGRAM S PINO UT A 54H/74H101 JK EDGE-TRIGGERED FLIP-FLOP (with A N D - O R Inputs D ESC R IP TIO N — The '101 is a high speed J K negative edge-triggered flipflop. The AND-OR gate inputs are inhibited while the clock input is LOW.	OCR Scan	PDF	Got377s 54H/74H101 54/74H 74H101
54H106FM Abstract: 74H106DC Text: 106 CONNECTION DIAGRAM PIN O U T A 54H/74H106 C If o r t DUAL JK E D G E -T R IG G E R E D F LIP -F LO P W ith S e p a ra te S ets, C le a r an d C lo cks DESCRIPTION — The ’106 is a high speed J K negative edge-triggered flipflop. It features individual J, K, clock and asynchronous set and clear inputs	OCR Scan	PDF	54H/74H106 54/74H 54H106FM 74H106DC
TS 4140 Abstract: 1235AC Text: 102 CO NNECTIO N DIAGRAMS PINOUT A 54H/74H102 C’ / î" ? ' 3 JK EDGE-TRIGGERED FLIP-FLOP With AND Inputs DESCRIPTION — The ’102 is a high speed JK negative edge-triggered flipflop. It features gated JK inputs and an asynchronous Clear input. The AND	OCR Scan	PDF	54H/74H102 54/74H TS 4140 1235AC
IC LA 4138 Abstract: No abstract text available Text: 101 CONNECTION DIAGRAMS P IN O U T A 54H/74H101 0 JK EDGE-TRIGGERED FLIP-FLOP with A N D -O R Inputs DESCRIPTION — The '101 is a high speed J K negative edge-triggered flipflop. The A N D -O R gate inputs are inhibited w hile the clo ck input is LOW. When the clo ck goes HIGH, the inputs are enabled and data will be accepted.	OCR Scan	PDF	54H/74H101 54/74H IC LA 4138
S54H108F Abstract: N74H108F N74H108N Text: 54H/74H108 DESCRIPTION The “ 108” is a Dual JK N egative EdgeT rig g e re d F lip -F lo p w ith in d iv id u a l JK and d ire c t Set inputs, and_com m on C lo c k and Reset inputs. T he Set S d and R eset (R d ) are asyn ch ro n o u s a ctive LO W inpu ts. W hen	OCR Scan	PDF	54H/74H 54S/74S 54LS/74LS S54H108F N74H108F N74H108N
N74H106F Abstract: N74H106N S54H106F S54H106W Text: 54H/74H106 DESCRIPTION Th e “ 106” is a Dual JK N egative EdgeT rig g e re d F lip-F lo p w ith individual JK, C lock, d ire c t Set and d ire c t Reset inputs. The Set S d and Reset (R d > are a s y n c h ro no us active LO W inpu ts. W hen LOW, the y	OCR Scan	PDF	54h/74h106 54H/74H 54S/74S 54LS/74LS N74H106F N74H106N S54H106F S54H106W
74H101 Abstract: N74H101F N74H101N S54H101F S54H101W Text: 54H/74H101 LOGIC SYMBOL A 5 DESCRIPTION The “ 101” is a JK N egative E dge -T rig gere d F lip-F lo p fe a tu rin g A N D -O R gated_JK in puts and a d ire c t Set inpu t. Th e Set S d is an a s y n c h ro n o u s active LOW input. W hen LOW, the So ove rrides th e c lo c k and data	OCR Scan	PDF	54H/74H101 54H/74H 54S/74S 54LS/74LS 74H101 N74H101F N74H101N S54H101F S54H101W

74H102 Abstract: 10mAVCC ScansUX995 Text: FAIRCHILD HIGH SPEED TTL/SSI . 9H102/54H102, 74H102 JK EDGE TRIGGERED FLIP-FLOP WITH AND INPUTS DESCRIPTION — The HSTTL/SSI 9H 102/54102, 74H102 is a High Speed JK Negative Edge Triggered flip-flop. They feature gated JK inputs and an asynchronous clear input. The A N D gate inputs are inhibited while the clock input is LOW; when the clock goes H IG H , the inputs are	OCR Scan	PDF	9H102/54H102, 74H102 9H102/54102, 10mAVCC ScansUX995
d146 Abstract: RS latch 74LS78 74LS114 7475 D latch d147 CI 74196 74LS112 7475 data latch fairchild 9314 Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 A « — 2 4— J. So Q 9— J Q U » CP CP o 1— 10 ¿ So CD 0—3 8_ K Ä Q Co —I I_ Vcc = Pin 14 GND = Pin 7 in Ü Q UJ EDGE-TRIGGERED 9 O (9 D58 54H/74H106 D59b 54H/74H108	OCR Scan	PDF	54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54LS/74LS279 93L14 54LS/74LS196 d146 RS latch 74LS78 74LS114 7475 D latch d147 CI 74196 74LS112 7475 data latch fairchild 9314
74H101 Abstract: 54H101 54H101FM 74H101DC 74H101FC 74H101PC 74hcl Text: 101 CO N N ECTIO N DIAGRAMS P IN O U T A 54H/74H101 0 JK EDGE-TRIGGERED FLIP-FLOP with AND-OR Inputs D E S C R IP T IO N — The '101 is a high speed J K negative edge-triggered flip flop. T he A N D-O R gate inputs are inhibited while the clock input is LOW.	OCR Scan	PDF	54H/74H101 54/74H 74H101 54H101 54H101FM 74H101DC 74H101FC 74H101PC 74hcl
Untitled Abstract: No abstract text available Text: 103 CONNECTION DIAGRAM P IN O U T A / / Ls> ^54H/74H103 DUAL JK EDGE-TRIGGERED FLIP-FLOP W ith Separate Clears and Clocks DESCRIPTION— The '103 is a high speed J K negative edge-triggered flipflop. It features individual J, K, clo ck and asynchronous clear inputs to each	OCR Scan	PDF	54H/74H103 54/74H
74H108 Abstract: clock schematic V126 ScansUX995 Text: FAIRCHILD HIGH SPEED TTL/SSI . 9H108/54H108, 74H108 DUAL JK EDGE TRIGGERED FLIP-FLOP WITH SEPARATE PRESETS AND A COMMON CLEAR AND CLOCK D E S C R IP T IO N — T h e H S T T L /S S I 9 H 1 0 8 /5 4 H 1 0 8 , 7 4 H 1 0 8 is a H igh Speed J K N eg ative Edge Trig g e re d f lip -flo p . T h e y fe a tu re in d iv id u a l J ,K ,	OCR Scan	PDF	9H108/54H108, 74H108 clock schematic V126 ScansUX995
74H10 Abstract: ScansUX994 Text: FAIRCHILD HIGH SPEED TTL/SSI . 9H10/54H10, 74H10 TRIPLE 3-INPUT NAND GATE SCH EM ATIC DIA G R A M EACH G ATE LOGIC A N D CO NNECTIO N D IA G R A M DIP (TOP VIEW ) F LA TPA K (TOP VIEW ) 14 Ue { 13 12 11 10 9 5rJ rb I GNO L U L ilL U L llU L llL J Positive lo gic: Y = A B C	OCR Scan	PDF	9H10/54H10, 74H10 9H10XM/54H10XM 9H10XC/74H10XC availabl-40 280S7 ScansUX994
H103 Abstract: S54H103F cock N74H103F N74H103N S54H103W Text: 54H/74H103 LOGIC SYMBOL DESCRIPTION The ‘'103" is a D ual JK N egative EdgeT rig gered F lip-F lo p w ith separate^ C lock and d ire c t Reset inputs. T h e R eset R d is an a syn ch ro n o u s a ctive LO W inpu t. W hen LOW, the R d ove rrides the C lock and data	OCR Scan	PDF	N74H103N N74H103F S54H103F S54H103W 54H/74H 54S/74S 54LS/74LS 54H/74H 54S/74S H103 S54H103F cock N74H103N S54H103W
MC3100 Abstract: MC3005L MC3005F MC3105F MC3105L Text: / TRIPLE 3-INPUT "NANO" GATE \| V MTTL III MC3100/3000 series MC3105F * MC3005F MC3105L * MC3005L,P 54H10J (74H10J,N) 1 / 3 O F C IR C U IT SHOWN T h is package consists o f th re e 3-in p u t N AN D gates. Each gate m ay b e used as an inverter, o r tw o gates	OCR Scan	PDF	MC3105F MC3005F MC3105L MC3005L 54H10J) 74H10J MC3100/3000 MMO61B0 O7000 DSP56002 MC3100 MC3105F MC3105L
dy 255 Abstract: 74s405 H R C M F 2J 225 Fairchild 9960 nixie driver 9614 line driver ci 8602 gn block diagram FJH211 Fairchild msi cul9960 variable frequency circuit diagram using IC 555 Text: IN THE, BOSTON - 6 17- 4 4 * A SUBSIDiA) ./ OF DUCOMMUN INCORPOfiATED S, MASS vw . JU N E 1 97 S Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the	OCR Scan	PDF
7410PC Abstract: 74LS10PC NAND Gate 3-Input 7410 7410P 7410DC 74LS10DC 5410FM 74H10PC 74LS10P 74S10PC Text: 10 C O N N E C T IO N D IA G R A M S P IN O U T A "54/7410 ^ 4 H /7 4 H 1 0 J-'/osl’ K54S /74S 10 û/'o ^ 7 > ^ 4 L S /7 4 L S 1 0 ^ 7 7 TRIPLE 3-INPUT NAND GATE O R D E R IN G C O D E: See S e ctio n 9 PIN PKGS C O M M E R C IA L G R A D E M ILITA R Y G R A D E	OCR Scan	PDF	4H/74H10^ 54S/74S10 4LS/74LS10i 7410PC, 74H10PC 74S10PC, 74LS10PC 7410DC, 74H10DC 74S10DC, 7410PC 74LS10PC NAND Gate 3-Input 7410 7410P 7410DC 74LS10DC 5410FM 74LS10P 74S10PC

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74H10 Search Results

74H10 Result Highlights (2)

74H10 Price and Stock

Rochester Electronics LLC 74H10DC

Rochester Electronics LLC 74H101PC

Rochester Electronics LLC SN74H102N

Cynergy3 Components LLF74H100RN

Cynergy3 Components TSF74H100DN

74H10 Datasheets (31)

74H10 Datasheets Context Search

7472 PIN DIAGRAM

NAND Gate 3-Input 7410

74H106

121122

CD 76 13 CP

CD 76 13 CP

74H103

74H101

54H106FM

TS 4140

IC LA 4138

S54H108F

N74H106F

74H101

74H102

d146

74H101

Untitled

74H108

74H10

H103

MC3100

dy 255

7410PC