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    74HC10 Search Results

    74HC10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC107P-E Renesas Electronics Corporation HD/RD74HC Series Visit Renesas Electronics Corporation
    74HC109FPEL-E Renesas Electronics Corporation HD/RD74HC Series, , / Visit Renesas Electronics Corporation
    74HC10FPEL-E Renesas Electronics Corporation HD/RD74HC Series Visit Renesas Electronics Corporation
    74HC10P-E Renesas Electronics Corporation HD/RD74HC Series Visit Renesas Electronics Corporation
    74HC109P-E Renesas Electronics Corporation HD/RD74HC Series Visit Renesas Electronics Corporation
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    74HC10 Price and Stock

    Texas Instruments SN74HC10DR

    IC GATE NAND 3CH 3-INP 14SOIC
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    Texas Instruments SN74HC109D

    IC FF JK TYPE DUAL 1BIT 16SOIC
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    DigiKey SN74HC109D Tube 3,840 1
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    Texas Instruments SN74HC10QDREP

    IC GATE NAND 3CH 3-INP 14SOIC
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    Nexperia 74HC10D-Q100J

    IC GATE NAND 3CH 3-INP 14SO
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    Nexperia 74HC109D,653

    IC FF JK TYPE DUAL 1BIT 16SO
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    Find more 74HC10 price and stock on Findchips.com

    74HC10 Datasheets (86)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74HC10 Philips Semiconductors Triple 3-Input NAND Gate Original PDF
    74HC107 Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HC107D Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HC107D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC107D,652 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger ; Fmax: 78 MHz; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 16@5V ns; Voltage: 2.0-6.0 V; Package: SOT108-1 (SO14); Container: Bulk Pack, CECC Original PDF
    74HC107D,653 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger ; Fmax: 78 MHz; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 16@5V ns; Voltage: 2.0-6.0 V; Package: SOT108-1 (SO14); Container: Reel Pack, SMD, 13", CECC Original PDF
    74HC107DB Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HC107DB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC107DB,112 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger ; Fmax: 78 MHz; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 16@5V ns; Voltage: 2.0-6.0 V; Package: SOT337-1 (SSOP14); Container: Tube Original PDF
    74HC107DB,118 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger ; Fmax: 78 MHz; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 16@5V ns; Voltage: 2.0-6.0 V; Package: SOT337-1 (SSOP14); Container: Reel Pack, SMD, 13" Original PDF
    74HC107DB-T Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HC107DB-T Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC107D-Q100 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger Original PDF
    74HC107D-Q100J NXP Semiconductors 74HC107D-Q100 - 74HC107D-Q100 - Dual JK flip-flop with reset; negative-edge trigger Original PDF
    74HC107D-T Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HC107D-T Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC107DW Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Original PDF
    74HC107N Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74HC107N Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC107N,652 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger ; Fmax: 78 MHz; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 16@5V ns; Voltage: 2.0-6.0 V; Package: SOT27-1 (DIP14); Container: Bulk Pack, CECC Original PDF

    74HC10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74HC109

    Abstract: No abstract text available
    Text: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features


    Original     		PDF CD54/74HC109, CD54/74HCT109 SCHS140A HC109 HCT109 SCLA008 SZZU001B, SDYU001N, SCET004, SCAU001A, 74HC109

    CD74HCT107

    Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002


    Original     		PDF HC107 HCT10 CD54/74HC107, CD54/74HCT107 SCHS139B HC107 HCT107 CD74HCT107 CD54HC107F3A CD54HCT107F3A CD74HC107E HCT10

    HC-107

    Abstract: HC107
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139A Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2000 Features


    Original     		PDF HC107 HCT10 CD54/74HC107, CD54/74HCT107 SCHS139A HC107 HCT107 HC-107

    Untitled

    Abstract: No abstract text available
    Text: 74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev. 3 — 18 November 2013 Product data sheet 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock CP and reset (R) inputs and complementary Q and Q


    Original     		PDF 74HC107; 74HCT107 74HCT107 HCT107

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140B Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised December 2002


    Original     		PDF CD54/74HC109, CD54/74HCT109 SCHS140B HC109 HCT109 CD74H CT109) 8415001EA CD54HC109F3A

    74hct10

    Abstract: 74HC10
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor


    Original     		PDF CD54/74HC10, CD54/74HCT10 SCHS128A HCT10 HCT10 SDYA012 SN54/74HCT SCLA011 SCLA008 SZZU001B, 74hct10 74HC10

    HCT109 harris

    Abstract: 74HCT109
    Text: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features


    Original     		PDF CD74H CT109) CD54/74HC109, CD54/74HCT109 SCHS140A HC109 HCT109 HCT109 harris 74HCT109

    74HC107PW

    Abstract: No abstract text available
    Text: 74HC107-Q100; 74HCT107-Q100 Dual JK flip-flop with reset; negative-edge trigger Rev. 1 — 18 November 2013 Product data sheet 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock CP and reset (R) inputs and complementary Q


    Original     		PDF 74HC107-Q100; 74HCT107-Q100 74HCT107-Q100 HCT107 74HC107PW

    CD74HC109E

    Abstract: HC109 C109 CD54HC109F3A CD54HCT109F3A
    Text: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140B Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised December 2002


    Original     		PDF CD74H CT109) CD54/74HC109, CD54/74HCT109 SCHS140B HC109 HCT109 CD74HC109E C109 CD54HC109F3A CD54HCT109F3A

    74HCT10

    Abstract: No abstract text available
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor


    Original     		PDF CD54/74HC10, CD54/74HCT10 SCHS128A HCT10 HCT10 59628984301CA CD54HCT10F3A 5962View 8984301CA 74HCT10

    74HC107

    Abstract: No abstract text available
    Text: Technical Data CD54/74HC107 CD54/74HCT107 File N u m b e r 1722 High-Speed CMOS Logic Dual J-K Flip-Flop with Reset N egative-E d g e T rigger Type Features: • zr GND * 7 v c c *14 92CS- 594 16 H y s te re s is o n c lo c k in p u ts fo r im p ro v e d n o is e im m u n ity a n d in c re a s e d


    OCR Scan     		PDF CD54/74HC107 CD54/74HCT107 CD54/74HCT107 54/74HC 54/74HCT 74HC107

    74hc10

    Abstract: 74HCT10
    Text: Technical Data_ CD54/74HC10 CD54/74HCT10 F ile N u m b e r 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Features: • B u ffe re d inpu ts • Typical propagation delay = 8 ns @ V'cc = 5 V, C L = 15 pF, I A = 25° C FUNCTIONAL DIAGRAM AND TERMINAL ASSIGNMENT


    OCR Scan     		PDF CD54/74HC10 CD54/74HCT10 54/74H 54LS/74LS D54HC10 74HCT 54HCT 54/74HC 54/74HCT 74hc10 74HCT10

    74HC109

    Abstract: M74HC109 54HC 74HC M54HC109
    Text: I SGS-THOMSON M 54HC109 M 74HC109 RfflDMO IIL[l g,0, ®RÖD i DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX = 60 MHz (TYP.) at VCC= 5V ■ LOW POWER DISSIPATION Ice = 2 (MAX.) at TA = 25°C ■ HIGH NOISE IMMUNITY VNIH = V NIL = 28% Vcc (MIN.)


    OCR Scan     		PDF M54HC109 M74HC109 54/74LS109 M54/74HC109 M54/74HC109 S-10170 74HC109 M74HC109 54HC 74HC

    74HC107

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC107 Dual J-K Flip-Flop w ith Reset High-Performance Silicon-Gate C M O S The M C 54/74H C 10 7 is id en tica l in p in o u t to the LS107. The device in p u ts are co m p a tib le w ith standard C M O S o u tp u ts ; w ith p u llu p resistors, they are c o m p a tib le


    OCR Scan     		PDF MC54/74HC107 54/74H LS107. HC107 MC54/74HC107 74HC107

    74hct10

    Abstract: 74HC10 PF7A L68G
    Text: G Technical Data. E SOLI» STATE 01 j>r| 3fl7SDfll 0G114SS 4 - T ^ 3 - - Z I CD54/74HC10 CD54/74HCT10 File Number 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Feature«: • Buffered inputs a Typical propagation delay = 8ns


    OCR Scan     		PDF 0G114SS CD54/74HC10 CD54/74HCT10 RCA-CD54/74HC10 54HCT/74HCT 54LS/74LS CD54H1 54HCT 74HCT 74hct10 74HC10 PF7A L68G

    Untitled

    Abstract: No abstract text available
    Text: blE J> MOTOROLA SC LOGIC MOTOROLA b3b72SS OCHlTBb T33 inom • SEMICONDUCTOR TECHNICAL DATA MC54/74HC109 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS T he MC54/74HC109 is id en tic a l in p in o u t to th e LS109. T he device in p u ts are


    OCR Scan     		PDF b3b72SS MC54/74HC109 MC54/74HC109 LS109. 54/74H

    YM 633

    Abstract: 74HC10
    Text: MO TO RO LA SC LOGIC MOTOROLA blE J> b3b7ESE MTI M0T4 • SEMICONDUCTOR TECHNICAL DATA MC54/74HC10 Triple 3-Inp u t N A N D Gate J SUFFIX CERAMIC CASE 632*08 High-Performance Silicon-Gate CM O S The MC54/74HC10 is identical in pinout to the LS10. The device inputs are com ­


    OCR Scan     		PDF MC54/74HC10 YM 633 74HC10

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SE M IC O N D U C TO R TECHNICAL DATA MC54/74HC109 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620*09 High-Performance Silicon-Gate CMOS T h e M C 5 4 /7 4 H C 1 0 9 is id e n tic a l in p in o u t to th e L S 1 0 9 . T h e d e v ic e in p u ts are


    OCR Scan     		PDF MC54/74HC109

    Untitled

    Abstract: No abstract text available
    Text: - Technical Data File N um b er 1667 CD54/74HC109 C D54/74HCT109 High-Speed CMOS Logic Duai J-K Flip-Flop with Set and Reset Type Features: 9 2 C S -36532 • Positive-Edge triggered • A s y n c h ro n o u s S et a n d Reset m 60 M Hz Typical M axim um C lo ck Frequency


    OCR Scan     		PDF CD54/74HC109 D54/74HCT109 54/74H 92CS-38533R2 92CS-38534R2 92CS-38535R2

    74HC107B1

    Abstract: No abstract text available
    Text: S G S -T H O M S O N l*[B} Q [iLi(gïï[HMO(gS M 54HC107 M 74HC107 DUAL J-K FLIP FLOP WITH CLEAR • HIGH SPEED fMAX = 75 MHz (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 2 nA (MAX.) AT Ta = 25 "C ■ HIGH NOISE IMMUNITY Vnih = V n il = 28 % V c c (MIN.)


    OCR Scan     		PDF 54HC107 74HC107 54/74LS107 54HC107F1R 74HC107B1R 107C1R 005447b 74HC107B1

    G0175

    Abstract: No abstract text available
    Text: Technical Data File N um ber CD54/74HC109 CD54/74HCT109 T-HL'-Q'l -01 1667 High-Speed CMOS Logic HARR IS S E M I C O N D S E CT OR to 27E D B 4 3 0 2 27 1 0 D 1 7 S M b 2 • HAS Dual J-K Flip-Flop with Set and Reset T yp e Features: 2J 2 K -H 2C P 12 VCC = 1 0


    OCR Scan     		PDF CD54/74HC109 CD54/74HCT109 92CS-38S3Z 54/74H 92CS-38533R2 92CS-38535R2 G0175

    74HC104

    Abstract: 74HC10490 D103 D106 D107 DI01 0560C
    Text: OCTAL SENSOR INTERFACE The 74HC10490 is a CMOS integrated circuit that is designed to interface to any type of mechanical contact or optical switch to eliminate contact bounce or transient signal effects. The 74H C 1 0490 provides eight sensor inputs that have internal pullups and


    OCR Scan     		PDF 74HC10490 74HC104 D103 D106 D107 DI01 0560C

    74HC10A

    Abstract: 74hc10 74HC10 equivalent
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC10 Triple 3-In p u t N A N D Gate J SUFFIX CERAMIC CASE 632*08 H igh -P e rfo rm a n ce S ilic o n -G a te C M O S The MC54/74HC10 is identical in pinout to the LS10. The device inputs are com ­ patible w ith standard CMOS outputs; w ith pullup resistors, they are compatible w ith


    OCR Scan     		PDF MC54/74HC10 51A-02 74HC10A 74hc10 74HC10 equivalent

    CXXXN

    Abstract: No abstract text available
    Text: MOTOROLA SC -CLOGIC} 02 b3b72Sa 0000170 5 ~T-4:b-07 -ü -7 MOTOROLA S E M IC O N D U C T O R TECHNICAL DATA MC54/74HC109 D ual J -K Flip-Flop w ith S e t and Reset J SUFFIX CERAM IC CA SE 620-09 High-Performance Silicon-Gate C M O S ' The M C 54/74H C 109 is identical in pinout to the LS109. The device inputs are


    OCR Scan     		PDF b3b72Sa MC54/74HC109 54/74H LS109. CHC109 CXXXN