74HC10 Search Results

74HC109

Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features

CD74HCT107

Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002

HC-107

Abstract: HC107
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139A Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2000 Features

Contextual Info: 74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev. 3 — 18 November 2013 Product data sheet 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock CP and reset (R) inputs and complementary Q and Q

74HC107

Contextual Info: Technical Data CD54/74HC107 CD54/74HCT107 File N u m b e r 1722 High-Speed CMOS Logic Dual J-K Flip-Flop with Reset N egative-E d g e T rigger Type Features: • zr GND * 7 v c c *14 92CS- 594 16 H y s te re s is o n c lo c k in p u ts fo r im p ro v e d n o is e im m u n ity a n d in c re a s e d

74hc10

Abstract: 74HCT10
Contextual Info: Technical Data_ CD54/74HC10 CD54/74HCT10 F ile N u m b e r 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Features: • B u ffe re d inpu ts • Typical propagation delay = 8 ns @ V'cc = 5 V, C L = 15 pF, I A = 25° C FUNCTIONAL DIAGRAM AND TERMINAL ASSIGNMENT

74HC109

Abstract: M74HC109 54HC 74HC M54HC109
Contextual Info: I SGS-THOMSON M 54HC109 M 74HC109 RfflDMO IIL[l g,0, ®RÖD i DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX = 60 MHz (TYP.) at VCC= 5V ■ LOW POWER DISSIPATION Ice = 2 (MAX.) at TA = 25°C ■ HIGH NOISE IMMUNITY VNIH = V NIL = 28% Vcc (MIN.)

74HC107

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC107 Dual J-K Flip-Flop w ith Reset High-Performance Silicon-Gate C M O S The M C 54/74H C 10 7 is id en tica l in p in o u t to the LS107. The device in p u ts are co m p a tib le w ith standard C M O S o u tp u ts ; w ith p u llu p resistors, they are c o m p a tib le

Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140B Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised December 2002

Contextual Info: Technical Data_ _ CD54/74HC10 CD54/74HCT10 F ile N u m b e r 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Features: • B u ffe re d inputs ■ Typical propagation delay = 8 ns @ V c c = 5 V, CL = 75 pF, 7"a = 25° C

74hct10

Abstract: 74HC10
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor

HCT109 harris

Abstract: 74HCT109
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features

74HC107PW

Contextual Info: 74HC107-Q100; 74HCT107-Q100 Dual JK flip-flop with reset; negative-edge trigger Rev. 1 — 18 November 2013 Product data sheet 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock CP and reset (R) inputs and complementary Q

74hct10

Abstract: 74HC10 PF7A L68G
Contextual Info: G Technical Data. E SOLI» STATE 01 j>r| 3fl7SDfll 0G114SS 4 - T ^ 3 - - Z I CD54/74HC10 CD54/74HCT10 File Number 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Feature«: • Buffered inputs a Typical propagation delay = 8ns

Contextual Info: blE J> MOTOROLA SC LOGIC MOTOROLA b3b72SS OCHlTBb T33 inom • SEMICONDUCTOR TECHNICAL DATA MC54/74HC109 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS T he MC54/74HC109 is id en tic a l in p in o u t to th e LS109. T he device in p u ts are

YM 633

Abstract: 74HC10
Contextual Info: MO TO RO LA SC LOGIC MOTOROLA blE J> b3b7ESE MTI M0T4 • SEMICONDUCTOR TECHNICAL DATA MC54/74HC10 Triple 3-Inp u t N A N D Gate J SUFFIX CERAMIC CASE 632*08 High-Performance Silicon-Gate CM O S The MC54/74HC10 is identical in pinout to the LS10. The device inputs are com ­

Contextual Info: MOTOROLA SE M IC O N D U C TO R TECHNICAL DATA MC54/74HC109 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620*09 High-Performance Silicon-Gate CMOS T h e M C 5 4 /7 4 H C 1 0 9 is id e n tic a l in p in o u t to th e L S 1 0 9 . T h e d e v ic e in p u ts are

Contextual Info: - Technical Data File N um b er 1667 CD54/74HC109 C D54/74HCT109 High-Speed CMOS Logic Duai J-K Flip-Flop with Set and Reset Type Features: 9 2 C S -36532 • Positive-Edge triggered • A s y n c h ro n o u s S et a n d Reset m 60 M Hz Typical M axim um C lo ck Frequency

74HC107B1

Contextual Info: S G S -T H O M S O N l*[B} Q [iLi(gïï[HMO(gS M 54HC107 M 74HC107 DUAL J-K FLIP FLOP WITH CLEAR • HIGH SPEED fMAX = 75 MHz (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 2 nA (MAX.) AT Ta = 25 "C ■ HIGH NOISE IMMUNITY Vnih = V n il = 28 % V c c (MIN.)

G0175

Contextual Info: Technical Data File N um ber CD54/74HC109 CD54/74HCT109 T-HL'-Q'l -01 1667 High-Speed CMOS Logic HARR IS S E M I C O N D S E CT OR to 27E D B 4 3 0 2 27 1 0 D 1 7 S M b 2 • HAS Dual J-K Flip-Flop with Set and Reset T yp e Features: 2J 2 K -H 2C P 12 VCC = 1 0

74HCT10

Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor

74HC104

Abstract: 74HC10490 D103 D106 D107 DI01 0560C
Contextual Info: OCTAL SENSOR INTERFACE The 74HC10490 is a CMOS integrated circuit that is designed to interface to any type of mechanical contact or optical switch to eliminate contact bounce or transient signal effects. The 74H C 1 0490 provides eight sensor inputs that have internal pullups and

74HC10A

Abstract: 74hc10 74HC10 equivalent
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC10 Triple 3-In p u t N A N D Gate J SUFFIX CERAMIC CASE 632*08 H igh -P e rfo rm a n ce S ilic o n -G a te C M O S The MC54/74HC10 is identical in pinout to the LS10. The device inputs are com ­ patible w ith standard CMOS outputs; w ith pullup resistors, they are compatible w ith

CXXXN

Contextual Info: MOTOROLA SC -CLOGIC} 02 b3b72Sa 0000170 5 ~T-4:b-07 -ü -7 MOTOROLA S E M IC O N D U C T O R TECHNICAL DATA MC54/74HC109 D ual J -K Flip-Flop w ith S e t and Reset J SUFFIX CERAM IC CA SE 620-09 High-Performance Silicon-Gate C M O S ' The M C 54/74H C 109 is identical in pinout to the LS109. The device inputs are