74LS 04 N Search Results

Contextual Info: LS T T L D N 74LS Series DN74LS04 D N 74L S 04 Dio74-LS 04 Hex Inverters P-1 • Description D N 7 4 L S 0 4 c o n ta in s six in v e rte r c irc u its. ■ Features • • L ow p o w e r c o n su m p tio n P d = 12m W ty p ic a l H igh sp ee d ( t pd = 9 .5 n s ty p ic a l)

Contextual Info: 1 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A S ig n e lic s Counters Logic Products FEATURES • Synchronous counting and loading • Two Count Enable inputs for nbit cascading • Positive edge-triggered clock • Asynchronous reset '160, ’161

74163 four bit binary counter

Abstract: LS162A 74163 pin configuration counter diagram 74161 162 bcd 74160 function table pin diagram of 74163 pin diagram of 74160 74LS163A equivalent LS160A
Contextual Info: 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A S ig n e tic s Counters '160, '162 BCD Decade Counter '161, '163 4-Bit Binary Counter Logic Products Product Specification FEATURES • Synchronous counting and loading • Two Count Enable Inputs for nbit cascading

74LS373PC

Abstract: 74LS373P e10s LOGIC DESCRIPTION OF 74LS373 LS 373 74LS373DC 54LS373DM 54LS373FM 74LS373FC 74LS373D
Contextual Info: 373 CONNECTIO N DIAGRAM PINOUT A / 54LS/74LS373 OCTAL TRANSPARENT LATCH W ith 3-S tate Outputs OE [7 Ü3 Vcc Oo U ï ï) 1 0 7 Do [ 2 jÜ D ? Di [7 13 De 01 [T ïi)0 6 02 (T 1 5 ] 05 Ds [ 7 ï ï d 3 [T 13] d » o 3 |T T U 04 G ND ¡10 DESCRIPTION — The ’373 consists o f eight latches w ith 3-state outputs for

74170PC

Abstract: oc75 54170DM 54170FM 54LS170DM 74170DC 74170FC 74LS170DC 74LS170FC 74LS170PC
Contextual Info: / — 7 Q - u / ~ u / _ CO NNECTIO N DIAGRAM PINOUT A 54/74170 54LS /74LS 170 4 X 4 REGISTER FILE Dz [T 16] V cc □3 [2 T |]D i W ith O p e n -C o lle c to r O utputs D 4 [I u ] W Ao [7 Ï5 ] W Ai RAi 12] WE RAo |T DESCRIPTION — T he ’170 contains 16 high speed, low power, transparent

74256

Abstract: ttl 74256 74LS256 demultiplexer 74ls 1N3064 1N916 74LS N74LS256D N74LS256N
Contextual Info: 74LS256 S ignetics Latch Dual 4-Bit Addressable Latch Product Specification Logic Products FEATURES • C o m b in e s d u a l d e m u ltip le x e r a nd 8 -b it la tc h TYPE T Y P IC A L P R O P A G A TIO N D ELAY T Y P IC A L SU PPLY C U R R E N T T O T A L

Contextual Info: 377 CO NNECTIO N DIAGRAM PINOUT A 54LS/74LS377 b / / S V 3 OCTAL D FLIP-FLOP With Common Enable and Clock DESCRIPTION — The '377 is an 8-bit register built using advanced low power S chottky technology. This register consists of eight D-type flip -flop s with a

ttl 74164

Abstract: 74164 14 PIN DIAGRAM two 74164 74164 74164 ttl 74LS164 af02000s 1N916 74LS LS164
Contextual Info: 74164 , LS 164 S ig n e tic s Shift Registers 8-Bit Serial-ln Parallel-O ut S h ift R egister Product Specification Logic P roducts FEATURES • • • • Gated serial Data inputs Typical s h ift frequency o f 36MHz Asynchronous Master Reset Fully buffered C lock and Data

M74LS682P

Abstract: 682P 683P
Contextual Info: MITSUBISHI LSTTLs M74LS682P v * o i # > fJ 8 -B IT M A G N ITU D E COMPARATOR DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74L S 68 2P is a semiconductor integrated circuit con­ taining tw o 8 -bit words comparator functions. O U TP U T • ~ W O p>0 -

ic 74198

Abstract: sn 74198 74198
Contextual Info: LOGIC SYMBOL 54/74198 3 DESCRIPTION FEATURES The “ 198” is a 8 -Bit B idirectio nal Universal Shift R egiste r useful in a w ide varie ty of a p ­ plications. As a high speed m ultifunctional sequential building block, it may be used in seria l-seria l, s eria l-pa rallel, pa rallel-se rial,

74LS373PC

Contextual Info: 373 CO NNECTIO N DIAGRAM PINOUT A V54LS/74LS373 o il / ^ OCTAL TRANSPARENT LATCH With 3-State Outputs DESCRIPTION — The ’373 consists o f eight latches w ith 3-state outputs for bus organized system applications. The flip -flop s appear transparent to the

1P2M

Abstract: 74LS242 74LS243 74S242 74S243 LS243 N74LS242N N74LS243N S243
Contextual Info: 74LS242, LS243, S242, S243 Signetics Transceivers '242 Quad Inverting Transceiver 3-State '243 Quad Transceiver (3-State) Product Specification Logic Products T Y P IC A L P R O P A G A TIO N D ELAY TY P IC A L SU PP LY C U R R E N T (T O T A L ) 74LS 242

74LS04 fan-out

Abstract: 7404PC 74LS04 pinout ls 7404 74LS04PC pin diagram of 7404 74ls04 hex inverter 74LS04P 74LS04* hEX INVERTER 74LS04 Hex Inverter definition
Contextual Info: 04 C O N N E C T IO N D IA G R A M S P IN O U T A •n *''54/7404 O 'n i> & ¡'54H/74H04 ; ■■ ^ 4 S /7 4 S 0 4 / " O /5 4 S /7 4 S 0 4 A ^ 4 L S /7 4 L S 0 4 G 3 E Œ Œ [I Œ d , - /- HEX INVERTER PKGS OUT C O M M E R C IA L G RADE M ILITA R Y G RADE

cem wax a

Contextual Info: 74LS620, LS623 Signetics Transceivers 'LS620 Inverting Octal Bus Transceiver 3-State 'LS623 Non-Inverting Octal Bus Transceiver (3-State) Product Specification Logic Products FEATURES • Octal bidirectional bus interface • 3-State buffer outputs - LS620, inverting

ST 1076

Abstract: SN74LS214 LCC4270 SN74LS215
Contextual Info: 54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS PIN A SSIG N M EN TS TO P VIEW S R A N D O M -A C C E SS M E M O R IE S Vç c A D H 207 W OE 1/01 V w of 1/01 1/02 1/03 E D G E -T R IG G E R E D W R IT E C O N T R O L 2 5 6 4 -B IT W O RDS C O M M O N I/O PORTS

74LS04 fan-out

Abstract: 7404PC 74LS04PC 74LS04 pinout 74s04p 74Ls04 fanout 74ls04 hex inverter 74LS04* hEX INVERTER 74LS04P 7404FC
Contextual Info: 04 CO NNECTIO N DIAGRAMS PINOUT A ^ 4 /7 4 0 4 ¡54H/74H04 ^ 4S /7 4 S 0 4 /54S/74S04A ^4LS/74LS04 / r Œ Œ [I Œ - 6 3 HEX INVERTER g n d ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C

S-R flip flop clock

Abstract: sr flip flop PIN DIAGRAM
Contextual Info: 323 / ^ 54LS/74LS323 Olb CO NNECTIO N DIAGRAM PINOUT A -1 4 ° 8-BIT UNIVERSAL SHIFT/STO RAG E REGISTER With S ynchronous Reset and C om m on I/O Pins DESCRIPTION — The ’323 ¡s an 8-bit universal shift/storage register w ith 3state outputs. Its fu n ctio n is sim ilar to the ’299 with the exception of Syn­

74LS373 PIN CONFIGURATION AND SPECIFICATIONS

Abstract: 74LS374 pin configuration 74LS374 74LS373 74ls373 LOGIC OF 74LS373 74LS373 pin configuration 74L5374 pin configuration 74LS373 74L5373 74LS373 40 pin 74LS374
Contextual Info: 74LS373, 74LS374, S373, S3 74 Signetics Latches/Flip-Flops '373 Octal Transparent Latch With 3-State Outputs '374 Octal D Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES T Y P IC A L P R O P A G A TIO N D E LAY TYPE • 8-bit transparent latch — '373

74LS293 Asynchronous counter

Abstract: 54ls293 74LS293 74LS293 pin 74LS N74LS293D N74LS293N
Contextual Info: Signetics 74LS293 Counter 4-Bit Binary Ripple C ounter Product Specification Lo g ic P rod ucts DESCRIPTION The '293 is a 4-bit ripple type binary counter. The device consists o f four master-slave flip-flops internally con­ nected to provide a divide-by-two sec­

16 bit comparator 74ls

Abstract: 8bit counter 74ls successive approximation 54LS502DM 54LS502FM 74LS502FC 74LS502PC 74LS502
Contextual Info: 502 CO NNECTIO N DIAGRAM PINOUT A {(Q^ 54LS /74LS 502 8-B IT SUCCESSIVE APPR O XIM ATIO N REGISTER DESCRIPTION — The ’LS502 is an 8-bit register w ith the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Com plete (CC signal coincident with storage of the eighth

Contextual Info: 54LS/74LS299 LOGIC SYMBOL DESCRIPTION FEATURES The "299" Is an 8-Bit Bidirectional Universal S h ift/S to ra g e R e g iste r w ith a 3 -sta te bidirectional Input/Output port. The register has four operating modes: shift right, shift left, parallel load, and hold do nothing . The

74165PC

Abstract: 74165 truth table 74LS165PC 74165DC 74LS165 74ls165d 7416 74165 54165DM 54165FM
Contextual Info: 165 C O NNECTIO N DIAGRAM P IN O U T A .« i/7 4 1 6 5 S 5 4 L S /7 4 L S 1 6 5 ' 0 ' / s / ^ * 3 7 8-B IT PAR ALLEL-TO -SER IAL CONVERTER 1 DESCRIPTION — Th e ’ 165 is a n 8 -b it pa ra lle l load or se ria l-in re g is te r w ith c o m p le m e n ta ry o u tp u ts a va ila b le fro m th e last stage. Parallel in p u tin g o c c u rs

74LS138PC

Abstract: 74LS138P 54S138DM 74S138PC demultiplexer 3 to 8 truth table 74LS138 connection for 74LS138 demultiplexer 74ls 74S138DC 74S138
Contextual Info: 138 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S138 ^ r 54LS/74LS138 &I&C n G c-s> Ao 1-OF-8 DECODER/DEMULTIPLEXER • • • • S C H O T T K Y P R O C E SS FO R H IG H SPEED D E M U L T IP L E X IN G C A P A B ILIT Y M U LT IP L E IN P U T ENABLE FO R EASY EXPANSIO N

Contextual Info: 322 I Ì 4»4LS/74LS322 I CO NNECTIO N DIAGRAM PINOUT A o ^ 8-BIT SERIAL/PARALLEL REGISTER (With Sign Extend DESCRIPTION — The ’322 is an 8-bit shift register w ith provision for either serial or parallel loading and with 3-state parallel outputs plus a bi-state serial