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    74LS373 PIN DIAGRAM Search Results

    74LS373 PIN DIAGRAM Result Highlights (2)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LS373NE4
    		Texas Instruments Octal D-type Transparent Latches with 3-state Outputs 20-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74LS373N
    		Texas Instruments Octal D-type Transparent Latches with 3-state Outputs 20-PDIP 0 to 70 Visit Texas Instruments Buy

    74LS373 PIN DIAGRAM Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    SN74LS573

    Contextual Info: Advance Information SN54LS573/SN74LS573 OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS G EN E R A L DESCRIPTION - The 54LS/74LS573 is a High-Speed Octal Latch with Buffered Common Latch Enable LE and Buffered Common Output Enable (OE) inputs. This device is functionally identical to the 54LS/74LS373, but has different pin­


    OCR Scan     		SN54LS573/SN74LS573 54LS/74LS573 54LS/74LS373, 54LS/74LS373 SN74LS573 PDF

    74LS374 74LS373 74ls373

    Abstract: 74LS373 74LS373 40 pin 74LS374 pin diagram 74ls373 LOGIC OF 74LS373 74LS374 DATASHEET 8D213 LS373 SN54LSXXXJ
    Contextual Info: SN54/74LS373 SN54/74LS374 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus


    Original     		SN54/74LS373 SN54/74LS374 74LS373 74LS374 74LS374 74LS373 74ls373 74LS373 40 pin pin diagram 74ls373 LOGIC OF 74LS373 74LS374 DATASHEET 8D213 LS373 SN54LSXXXJ PDF

    LOGIC OF 74LS373

    Abstract: 74LS373 PIN CONFIGURATION AND SPECIFICATIONS LS 373 74LS374 pin configuration 74LS374 function latch 74ls 373
    Contextual Info: 74LS373, 74LS374, S373, S374 Signetics Logic Products I Latches/Flip-Flops FEATURES • 8-bit transparent latch — '373 • 8-blt positive, edge-triggered register — '374 • 3-State output buffers • Common 3-State Output Enable • Independent register and 3-State


    OCR Scan     		74S374 74LS373, 74LS374, 74LS373 105mA 116mA 74S373 74LS374 500ns LOGIC OF 74LS373 74LS373 PIN CONFIGURATION AND SPECIFICATIONS LS 373 74LS374 pin configuration 74LS374 function latch 74ls 373 PDF

    D flip-flop 74175 pin

    Abstract: 74LS78 74LS374 74ls373 93L38 74298 D150 D190 74LS374 74LS373 74ls373 D Flip-Flop
    Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 Vcc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| FI j j j SD SD J Q J C CP Q — e CP K >— 12 Q Q 5— 9 K CD CD LlI lil LiJ Lil LiTIU LzJ LlI üü bsJ QNO 9 3 4 li 5 D85 54LS/74LS373


    OCR Scan     		54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 /74LS573 93L34 D flip-flop 74175 pin 74LS78 74LS374 74ls373 93L38 74298 D150 D190 74LS374 74LS373 74ls373 D Flip-Flop PDF

    74L5373

    Abstract: 74L5374 74LS373 PIN CONFIGURATION AND SPECIFICATIONS 74LS374 pin configuration 74LS374 74LS373 74LS373 pin configuration 74S373 745373 74S374
    Contextual Info: Signetics 74LS373, 74LS374, S373, S374 Latches/Flip-Flops '373 Octal Transparent Latch With 3-State Outputs '374 Octal D Flip-Flop With 3-State Outputs Logic Products Product Specification FEATURES • 8-bit transparent latch — '373 • 8-bit positive, edge-triggered


    OCR Scan     		C006830S 1N916, 1N3064, 500ns 74L5373 74L5374 74LS373 PIN CONFIGURATION AND SPECIFICATIONS 74LS374 pin configuration 74LS374 74LS373 74LS373 pin configuration 74S373 745373 74S374 PDF

    IC 74ls373

    Abstract: 74LS373 74LS533 74LS373 40 pin SN74LS373N AM25LS533DC 74LS53 Ls373 pin diagram of IC 74LS373 sn54ls373j
    Contextual Info: Am25LS373 • Am54LS/74LS373 Am25LS533 • Am54LS/74LS533 Octal Latches with Three-State Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • 8 latches in a single package • Non-inverting 'LS373, inverting LS533 • Three-state outputs interlace directly with bus organized


    OCR Scan     		Am25LS373 Am54LS/74LS373 Am25LS533 Am54LS/74LS533 LS373, LS533 Am25LS Am54LS/74LS MIL-STD-883 Am25LS/54LS/74LS373 IC 74ls373 74LS373 74LS533 74LS373 40 pin SN74LS373N AM25LS533DC 74LS53 Ls373 pin diagram of IC 74LS373 sn54ls373j PDF

    LOGIC DESCRIPTION OF 74LS373

    Abstract: 74ls373 am8085 LS74 74LS373 40 pin 74LS533 54ls174 pad layout 74LS373 uses and functions 74LS53 74LS
    Contextual Info: Am25LS373 • Am54LS/74LS373 Am25LS533 • Am54LS/74LS533 Octal Latches with Three-State Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • 8 latches in a single package • Non-inverting 'LS373, inverting LS533 a Three-state outputs interlace directly with bus organized


    OCR Scan     		Am25LS373 Am54LS/74LS373 Am25LS533 Am54LS/74LS533 LS373, LS533 Am25LS Am54LS/74LS MIL-STD-883 Am25LS/54LS/74LS373 LOGIC DESCRIPTION OF 74LS373 74ls373 am8085 LS74 74LS373 40 pin 74LS533 54ls174 pad layout 74LS373 uses and functions 74LS53 74LS PDF

    74ls373 datasheet

    Abstract: ls374 motorola 74LS373 74LS374 74LS374 DATASHEET 74LS374 74LS373 74ls373 datasheet ls373 SN54/74LS373 74LS373 40 pin FAST AND LS TTL
    Contextual Info: SN54/74LS373 SN54/74LS374 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus


    Original     		SN54/74LS373 SN54/74LS374 74LS373 74LS374 74ls373 datasheet ls374 motorola 74LS374 DATASHEET 74LS374 74LS373 74ls373 datasheet ls373 SN54/74LS373 74LS373 40 pin FAST AND LS TTL PDF

    74LS374N

    Abstract: 74LS373N pin diagram of IC 74LS373 74ls373 buffer ic LD02S 74LS373 PIN CONFIGURATION AND SPECIFICATIONS 74LS374D 74s373n 74LS374 74LS373 74ls373 74S374N
    Contextual Info: Signetics 74LS373, 74LS374, S373, S374 Latches/Flip-Flops '373 Octal Transparent Latch With 3-State Outputs '374 Octal D Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES TY P IC A L PR O P A G A TIO N D E LA Y T Y P IC A L SU PP LY C U R R E N T


    OCR Scan     		74LS373, 74LS374, 500ns 500ns 1N916, 1N3064, 74LS374N 74LS373N pin diagram of IC 74LS373 74ls373 buffer ic LD02S 74LS373 PIN CONFIGURATION AND SPECIFICATIONS 74LS374D 74s373n 74LS374 74LS373 74ls373 74S374N PDF

    74LS374

    Contextual Info: M M O T O R O L A SN54/74LS373 SN54/74LS374 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The S N 54/74LS 373 consists of eight latches with 3-state outputs for bus


    OCR Scan     		54/74LS SN54/74LS374 74LS374 PDF

    pin diagram of IC 74LS373

    Abstract: IC TTL 74 ls 04 IC 74ls373 ls374 74LS374 74LS373 74ls373 pin diagram of IC 74LS374
    Contextual Info: Q M O T O R O L A SN54/74LS373 SN54/74LS374 D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 3 7 3 consists of eioht latches w ith 3-state outputs for bus organized system applications. The flipflops appear transparent to the data (data changes asynchronous^ )


    OCR Scan     		SN54/74LS374 pin diagram of IC 74LS373 IC TTL 74 ls 04 IC 74ls373 ls374 74LS374 74LS373 74ls373 pin diagram of IC 74LS374 PDF

    74ls373 parallel port

    Abstract: d92 02 74175 ttl pin diagram 74198 74ls175 pin diagram 74198 ttl 74LS374 D172 D173 9z17
    Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 F5I Fä| F I jjjjj j j b SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI l i l LiJ L il L iT I U LzJ Ll I üü bsJ QNO 9 3 4 5 D85


    OCR Scan     		54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 /74LS573 93L34 74ls373 parallel port d92 02 74175 ttl pin diagram 74198 74ls175 pin diagram 74198 ttl 74LS374 D172 D173 9z17 PDF

    MD74HCT373RE

    Abstract: MD74HCT373
    Contextual Info: Octal D-TypeTrgrtsparehtLatch February'85 Features CONNECTION DIAGRAM DIP TOP VIEW •High latch-ufirlmMyniJy * ’ ~*'‘ ’ •*" «' _ • High current outputs cah drive 30 LSTTL loads 1 20 U Vcc 19 =>o7 18 ] D , . Pa C 2 • Low power IS&-CMOS technology


    OCR Scan     		54/74LS373 MD54HGT373fic, MD74HCT373RE, MD74HCT373RE MD74HCT373 PDF

    74LS373 PIN CONFIGURATION AND SPECIFICATIONS

    Abstract: 74LS374 pin configuration 74LS374 74LS373 74ls373 LOGIC OF 74LS373 74LS373 pin configuration 74L5374 pin configuration 74LS373 74L5373 74LS373 40 pin 74LS374
    Contextual Info: 74LS373, 74LS374, S373, S3 74 Signetics Latches/Flip-Flops '373 Octal Transparent Latch With 3-State Outputs '374 Octal D Flip-Flop With 3-State Outputs Product Specification Logic Products FEATURES T Y P IC A L P R O P A G A TIO N D E LAY TYPE • 8-bit transparent latch — '373


    OCR Scan     		74LS373, 74LS374, 74LS373 74S373 105mA 74LS374 1N916, 1N3064, 500ns 74LS373 PIN CONFIGURATION AND SPECIFICATIONS 74LS374 pin configuration 74LS374 74LS373 74ls373 LOGIC OF 74LS373 74LS373 pin configuration 74L5374 pin configuration 74LS373 74L5373 74LS373 40 pin PDF

    D flip-flop 74175 pin

    Abstract: 74175 D flip flop D134 8-bit ttl latch 93L38 74LS573 ttl 7497 D187 D188 D190
    Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D187 9397, 7497 D188 93167, 74167 0189 54LS/74LS173 9 10 14 15 k h 12 Ü 13 IE 11 — 0 CE 9 - CP 10— 0 Ez 1 2 - Gy TC OE D190 54LS/74LS375 D194 54LS/74LS390 each half) 15 1 ,1 5 - CPo 4 ,1 2 -


    OCR Scan     		54LS/74LS173 54LS/74LS375 54LS/74LS390 54LS/74LS393 /74LS573 93L34 54LS/74LS259 93L38 54LS/74LS170 54ILS/74LS670 D flip-flop 74175 pin 74175 D flip flop D134 8-bit ttl latch 74LS573 ttl 7497 D187 D188 D190 PDF

    74LS93 P

    Abstract: TTL 74LS93 74293 pin diagram 74LS78 TTL 74293 74176 74293 74LS490 74LS93 74LS373
    Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| FI j j j SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI lil LiJ Lil LiTIU LzJ LlI üü bsJ QNO 9 3 4 li 5 D85


    OCR Scan     		54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS290 54LS/74LS293 74LS93 P TTL 74LS93 74293 pin diagram 74LS78 TTL 74293 74176 74293 74LS490 74LS93 74LS373 PDF

    74LS373PC

    Contextual Info: 373 CO NNECTIO N DIAGRAM PINOUT A V54LS/74LS373 o il / ^ OCTAL TRANSPARENT LATCH With 3-State Outputs DESCRIPTION — The ’373 consists o f eight latches w ith 3-state outputs for bus organized system applications. The flip -flop s appear transparent to the


    OCR Scan     		V54LS/74LS373 54/74LS 74LS373PC PDF

    74LS573

    Abstract: 74LS573 "LATCH" 74LS573 latch d flip-flop 93L28 D150 D177 D178 D181 D190
    Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D177 9328, 93L28 D178 54/7491 D179 54LS/74LS573 2 3 Do D i Da Q h - 13 CP Oh 4 5 6 7 Ds D e D ? D2 D a D4 Û2 O s 04 0 5 O e Q? 1 1 - LE 1 “O - 14 OE Oo Q i I 1I I I I I I 19 18 17 16 15 14 13 12


    OCR Scan     		93L28 54LS/74LS573 54LS/74LS352 54LS/74LS353 /74LS573 93L34 54LS/74LS259 93L38 54LS/74LS170 54ILS/74LS670 74LS573 74LS573 "LATCH" 74LS573 latch d flip-flop 93L28 D150 D177 D178 D181 D190 PDF

    74LS244 diagram

    Abstract: 74LS31 74LS373 Decoder pin BYU29 TMS32010 74ALS02 74ALS32 ADC80Z 74F245 74LS373
    Contextual Info: Chapter 5 Theory of Operation The AIB has three basic input/output I/O ports: an analog I/O port, an expansion I/O port, and an extended memory interface port. The analog input port consists of an anti-aliasing filter, a sample and hold circuit, and an analog-to-digital (A/D) converter. The analog output port consists of a digital-toanalog converter, a smoothing filter, an an optional audio output amplifier. The expansion input port provides sixteen buffered inputs, and the expansion output port


    Original     		PDF

    74191 8 bit

    Abstract: 7443 Flip-Flop D134 7443 d Flip-Flop 74LS42 74155 9B23 D135 93L38 93L11
    Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8


    OCR Scan     		74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 74191 8 bit 7443 Flip-Flop D134 7443 d Flip-Flop 74LS42 74155 9B23 D135 93L38 93L11 PDF

    74162

    Abstract: D129 74LS191 74192 pin diagram of 74163 74160 pin 74190 74LS162 74LS190 pins presettable digital clock
    Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| FI j j j SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI lil LiJ Lil LiTIU LzJ LlI üü bsJ QNO 9 3 4 5 D85 54LS/74LS373


    OCR Scan     		54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS163 54LS/74LS168 74162 D129 74LS191 74192 pin diagram of 74163 74160 pin 74190 74LS162 74LS190 pins presettable digital clock PDF

    74LS373PC

    Abstract: 74LS373P e10s LOGIC DESCRIPTION OF 74LS373 LS 373 74LS373DC 54LS373DM 54LS373FM 74LS373FC 74LS373D
    Contextual Info: 373 CONNECTIO N DIAGRAM PINOUT A / 54LS/74LS373 OCTAL TRANSPARENT LATCH W ith 3-S tate Outputs OE [7 Ü3 Vcc Oo U ï ï) 1 0 7 Do [ 2 jÜ D ? Di [7 13 De 01 [T ïi)0 6 02 (T 1 5 ] 05 Ds [ 7 ï ï d 3 [T 13] d » o 3 |T T U 04 G ND ¡10 DESCRIPTION — The ’373 consists o f eight latches w ith 3-state outputs for


    OCR Scan     		54LS/74LS373 74LS373PC 74LS373DC 74LS373FC 54/74LS 74LS373PC 74LS373P e10s LOGIC DESCRIPTION OF 74LS373 LS 373 74LS373DC 54LS373DM 54LS373FM 74LS373FC 74LS373D PDF

    7475 D latch

    Abstract: D146 D147 ci 7475 rs latch 74LS109 74LS78 74LS107 74LS114 7475 data latch
    Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| F I j j j SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI l i l LiJ L il L iT I U LzJ Ll I ü ü bsJ QNO 9 3 4 li


    OCR Scan     		54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS279 93L14 7475 D latch D146 D147 ci 7475 rs latch 74LS109 74LS78 74LS107 74LS114 7475 data latch PDF

    GD74LS373

    Contextual Info: GD54LS373/GD74LS373 OCTAL D-TYPE LATCHES; 3-STATE OUTPUTS COMMON OUTPUT CONTROL COMMON ENABLE Feautre • • • • • 8 Latches in a Single Package 3-State Bus-Driving Outputs Full Paralle-Access for Loading Buffered Control Inputs Clock/Enable input Has Hysteresis to Improve


    OCR Scan     		GD54LS373/GD74LS373 GD74LS373 PDF