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    74LS76 IC Search Results

    74LS76 IC Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74LS76AP-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation

    74LS76 IC Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74HC76

    Abstract: logic ic 74LS76 pin diagram pin diagram for IC 74ls76 74ls76 jk flip-flop logic symbol and truth table IC 74LS76 74LS76 IC M74HC76 M74HC76B1R 74Ls76 truth table M74HC76M1R
    Text: M54HC76 M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 65 MHz TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.)


    Original     		PDF M54HC76 M74HC76 54/74LS76 M54HC76F1R M74HC76M1R M74HC76B1R M74HC76C1R M54/74HC76 74HC76 logic ic 74LS76 pin diagram pin diagram for IC 74ls76 74ls76 jk flip-flop logic symbol and truth table IC 74LS76 74LS76 IC M74HC76 M74HC76B1R 74Ls76 truth table M74HC76M1R

    logic ic 7476 pin diagram

    Abstract: and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
    Text: 54/7476 54H/74H76 54LS/74LS76 DESCRIPTION ORDERING CODE PACKAGES PIN CONF. 2 The 74LS76 is a negative edge triggered flip-flop. The J and K inputs must be stable only one setup time prior to the HIGH-toLOW Clock transition. The Set Sd and Reset (Rd ) are asynchro­


    OCR Scan     		PDF 54H/74H76 54LS/74LS76 74H76 74LS76 54H/74H 54S/74S 54LS/74LS logic ic 7476 pin diagram and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80

    7476 truth table

    Abstract: 7476 logic diagram 74LS76P 7476PC 74ls76
    Text: NATIONA L SEMICOND -CLOGIO 02E D | b S O U S E 76 GGbBVSO t, | 3 T-ŸL- 0 7 -0 7 CONNECTION DIAGRAM PINOUT A 54/7476 54H/74H76 54LS/74LS76 DUAL JK FLIP-FLOP With Separate Sets, Clears and Clocks DESCRIPTION — The '76 and 'H76 are dual JK master/slave flip-flops with


    OCR Scan     		PDF 54H/74H76 54LS/74LS76 54/74H 54/74LS CLS76) 7476 truth table 7476 logic diagram 74LS76P 7476PC 74ls76

    74ls76 jk flip-flop logic symbol and truth table

    Abstract: 7476PC 7476 PIN DIAGRAM 7476 truth table 74LS76PC 74LS76 dual flip-flop pin diagram of 7476 74LS76D 74LS76DC Jk 74ls76 pin out
    Text: 76 CONNECTIO N DIAGRAM PINOUT A ^54/7476 OZZô/b> ^54H /74H 76 G f / c t l l/54LS/74LS76 DUAL JK FLIP-FLOP With Separate Sets, Clears and Clocks c p i [T DESCRIPTION — The ’76 and 'H76 are dual JK m aster/slave flip -flo p s with separate Direct Set, D irect Clear and Clock Pulse inputs fo r each flip -flop .


    OCR Scan     		PDF 54H/74H76 l/54LS/74LS76 54/74H 54/74LS CLS76) 74ls76 jk flip-flop logic symbol and truth table 7476PC 7476 PIN DIAGRAM 7476 truth table 74LS76PC 74LS76 dual flip-flop pin diagram of 7476 74LS76D 74LS76DC Jk 74ls76 pin out

    74LS112

    Abstract: 74112 74ls76 74112 FF JK 74S112 IS5038 74112+asynchronous+4bit+up+down+counter+using+jk+flip+flop
    Text: - 92 - Dual JK-FFs with Preset and Clear 74112 1 2 èhm. 74LS76 O * i f 7 - 4 7' ' — t ' 4 > 7 * - / V h ') ft m 0 « ] i^ li7 4 L S 7 6 ir e R - t su S AS AC ACT HC 30 100 80 175 125 80 21 22 MHz 20 16.5 5 6 5.0 8.0 20 20 ns 16.5 5 6.5 5.fr 8.0 20 20 ns


    OCR Scan     		PDF 74LS76 li74LS76Â 74LS112 74S112 74LS112 74112 74ls76 74112 FF JK 74S112 IS5038 74112+asynchronous+4bit+up+down+counter+using+jk+flip+flop

    74LS76P

    Abstract: 74LS76D IC 7476 pinout logic ic 7476 flip-flop pin diagram and pin diagram of IC 7476 logic ic 7476 pin diagram 7476PC 74H76 74LS76 pinout 74LS76 IC
    Text: 76 CO NNECTIO N DIAGRAM PINOUT A /54/7476 0 / / o / c^ ^S4H/74H76 Gf / ci 7 ^ 54LS/74LS76£ v / 6 / 6 DUAL JK FLIP-FLOP With Separate Sets, Clears and Clocks DESCRIPTION — The ’76 and 'H76 are dual JK m aster/slave flip -flo p s with separate Direct Set, D irect Clear and Clock Pulse inputs fo r each flip-flop.


    OCR Scan     		PDF S4H/74H76 54LS/74LS76£ 54/74H 54/74LS CLS76) 74LS76P 74LS76D IC 7476 pinout logic ic 7476 flip-flop pin diagram and pin diagram of IC 7476 logic ic 7476 pin diagram 7476PC 74H76 74LS76 pinout 74LS76 IC

    logic ic 74LS76 pin diagram

    Abstract: j-k flip flop 74ls76 IC 74LS76
    Text: LS TTL DN74LS Series DN74LS76 D N 74LS76 D ^ 74^ 7^ Dual J-K F lip -F lo p s with S e t and Reset • Description P -2 D N 7 4 L S 7 6 contains tw o negative-edge triggered J-K flip-flop circuits, each w ith independent clock-C P, J, K, and directcoupled set and reset input terminals.


    OCR Scan     		PDF DN74LS DN74LS76 74LS76 16-pin logic ic 74LS76 pin diagram j-k flip flop 74ls76 IC 74LS76

    MAX77100

    Abstract: IC74 IC-74
    Text: SANYO SEMICONDUCTOR CORP 53E TW OTb T> 0010S31 037 « T S A J r- H4>~ 0 7 — 0 7 MLC74HC76M No.3628 f CMOS High-Speed Standard Logic Dual J-K Flip-Flop with Reset and Set F e a tu re s • The MLC74HC76M consists of 2 identical J-K type flip-flops. • Uses CMOS silicon gate process technology to achieve operating speeds sim ilar to LS-TTL 74LS76


    OCR Scan     		PDF 0010S31 MLC74HC76M MLC74HC76M 74LS76) 54LS/74LS MLC74HC MAX77100 IC74 IC-74

    7476 truth table

    Abstract: 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram of 7476 S5476F PIN CONFIGURATION 7476 7476 7476 pin configuration
    Text: 54/7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76” is a D ual J K F lip -F lo p w ith in d iv id ­ ual J, K, C lock, S et and Reset inpu ts. Th e 7476 and 74H76 are p o sitive pulse trig g e re d flip -flo p s . JK in fo rm a tio n is loaded in to the m aster w h ile the C lock is H IG H and tra n s ­


    OCR Scan     		PDF 54H/74H76 54LS/74LS76 74H76 74LS76 7476 truth table 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram of 7476 S5476F PIN CONFIGURATION 7476 7476 7476 pin configuration

    pin diagram of 7476

    Abstract: 7476 FUNCTION TABLE 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 PIN DIAGRAM 7476 Jk 74ls76 pin out 74LS76 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476
    Text: 7476, LS76 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with Individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-trig­ gered. JK information is loaded into the


    OCR Scan     		PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 7476 FUNCTION TABLE 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 PIN DIAGRAM 7476 Jk 74ls76 pin out 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476

    pin diagram of 7476

    Abstract: 74LS76 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output Jk 74ls76 pin out 7476 FUNCTION TABLE 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
    Text: 7476, LS76 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the master while the Clock is HIGH and


    OCR Scan     		PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output Jk 74ls76 pin out 7476 FUNCTION TABLE 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram

    PIN CONFIGURATION 7476

    Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
    Text: 7476, LS76 Sjgnetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-trig­ gered. JK information is loaded into the


    OCR Scan     		PDF 74LS76 1N916, 1N3064, 500ns 500ns PIN CONFIGURATION 7476 pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476

    74LS76

    Abstract: flip-flop 74ls76 Jk 74ls76
    Text: SANYO SE MIC ONDU CT OR CORP ~ 1EE I | 7Ti707b GODEbbñ fe-07-o 7 IC74HG76M •*- . .v_\ *•» C M O S High-Speed Standard Logic _ LC74H C Series . Dual J-K Flip-Flop with Set and Reset Features • The LC74HC76M consists o f 2 identical J-K type flip-flops.


    OCR Scan     		PDF 7Ti707b IC74HG76M -07-o LC74H LC74HC76M 74LS76) 54LS/74LS 10sec LC74HC76. 74LS76 flip-flop 74ls76 Jk 74ls76

    logic ic 7476 pin diagram

    Abstract: logic ic 74LS76 pin diagram ic 74109 74LS107 74109 dual JK IC 74196 7476 Connection diagram 74LS109 ic 7474 pin diagram 7474 D latch
    Text: IO PO 10 ro o CO 00 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch - o to Item 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit RS Latch 4-Bit RS Latch 4-Bit RS Latch 4-Bit RS Latch 5477 54/7475 93L14 9314


    OCR Scan     		PDF 54LS/74LS77 54LS/74LS75 54LS/74LS197 93L14 54LS/74LS196 54LS/74LS279 54H/74H73, 54LS/74LS73 54LS/74LS107 logic ic 7476 pin diagram logic ic 74LS76 pin diagram ic 74109 74LS107 74109 dual JK IC 74196 7476 Connection diagram 74LS109 ic 7474 pin diagram 7474 D latch

    Jk 74ls76 pin out

    Abstract: 74LS76 pinout TTL 74ls76 74ls76 74ls series logic family j-k flip flop 74ls76 LC74HC76 LC74HC76M 74LS76 dual flip-flop
    Text: SANYO SE MIC ONDU CT OR CORP 1 2 E »"I 7Ti707b GQDEbbñ S tC 74HG76M r,: -.V . C M O S High-Speed Standard Logic L C 7 4 H C Senes 3035A Dual J -K Flip-Flop with Set and Reset 2186 Features • The LC 74H C 76M consists of 2 identical J-K type flip-flops.


    OCR Scan     		PDF 7clci70 LC74HG76M LC74HC LC74HC76M 74LS76) 54LS/74LS TaS85Â 10sec 035A-M16IC Jk 74ls76 pin out 74LS76 pinout TTL 74ls76 74ls76 74ls series logic family j-k flip flop 74ls76 LC74HC76 74LS76 dual flip-flop

    74HC76

    Abstract: logic ic 74LS76 pin diagram M74HC76
    Text: w # S G S -T H O M S O N k7Æ„ öiö g ®i[LI(g iO i M54HC76 M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX = 60 MHz (TYP. at VCc = 5V ■ LOW POWER DISSIPATION Ice = 2 inA (MAX.) at 25°C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS


    OCR Scan     		PDF M54HC76 M74HC76 54/74LS76 M54/74HC76 M54/74HC76 74HC76 logic ic 74LS76 pin diagram M74HC76

    74HC76

    Abstract: DIODE A7N 54HC 74HC M54HC76 M74HC76 M74HC76B1N
    Text: SGS-THOMSON M 54HC76 M74HC76 D M[l[LIl gTr[S (RÖD©i DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX = 60 MHz (TYP. at VCC= 5V ■ LOW POWER DISSIPATION Ice = 2 nA (MAX.) at 25°C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS 1 ■ BALANCED PROPAGATION DELAYS


    OCR Scan     		PDF M54HC76 M74HC76 54/74LS76 M54/74HC76 M54/74HC76 k50v- 74HC76 DIODE A7N 54HC 74HC M74HC76 M74HC76B1N

    74HC76

    Abstract: 54HC76 logic ic 74LS76 pin diagram Toggle flip flop IC
    Text: M 54HC76 M 74HC76 S G S -T H O M S O N 1 L0 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR HIGH SPEED = 65 MHz (TYP. AT Vcc = 5 V LOW POWER DISSIPATION Ice = 2 nA (MAX.) AT 25 °C OUTPUT DRIVE CAPABILITY 10LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE I Io h I = Iol = 4 mA (MIN.)


    OCR Scan     		PDF 54HC76 74HC76 10LSTTL 54/74LS76 M54/74HC76 74HC76 logic ic 74LS76 pin diagram Toggle flip flop IC

    M74HC76

    Abstract: No abstract text available
    Text: r z 7 S C S -T H O M S O N ^7# M54HC76 M 0 ^ sm ^iri«0 0 1 _M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR HIGHSPEED fMAX = 65 MHz (TYP. AT Vcc = 5 V LOW POWER DISSIPATION Ice = 2 ^iA (MAX.) AT 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTLLOADS SYMMETRICAL OUTPUT IMPEDANCE


    OCR Scan     		PDF M54HC76 M74HC76 54/74LS76 54HC76F1R 74HC76B1R M54/74HC76 M54/M74HC76 M74HC76

    74hc76

    Abstract: M74HC76
    Text: M54HC76 M74HC76 / = T S G S -T H O M S O N G * [K 3 Q i[L [i(g ^ @ iO (g S DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIGH SPEED fMAX = 60 MHz (TYP.) at VCC= 5V ■ LOW POWER DISSIPATION lCc = 2 nA (MAX.) at 25°C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS


    OCR Scan     		PDF M54HC76 M74HC76 54/74LS76 M54/74HC76 and35 M54/74HC76 74hc76 M74HC76

    74LS76 IC

    Abstract: TC74HC76AP IC 74LS76 AF4 equivalent TC74HC76A
    Text: TC74HC76AP/AF D U A L J - K F L I P - F L O P WI TH P R E S E T A N D C L E A R The TC74HC76A is a high speed CMOS J - K FL IP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation sim ilar to equivalent LSTTL while m aintaining the CMOS low power


    OCR Scan     		PDF TC74HC76AP/AF TC74HC76A TC74HC76AP/AF-3 TC74HC76AP/AF-4 74LS76 IC TC74HC76AP IC 74LS76 AF4 equivalent

    74LS76D

    Abstract: M74HC76
    Text: rrr s g s -th o m s o n Ä T # ms4 h c ? 6 R fflD O œ iL iO ÏÏM iD g i M 7 4 H C 7 6 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIG HSPEED fMAX = 65 MHz TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 2 jiA (MAX.) AT 25 °C ■ OUTPUT DRIVE CAPABILITY


    OCR Scan     		PDF 54/74LS76 M54/74Hhis 74LS76D M74HC76

    74hc76

    Abstract: M74HC76
    Text: SbE D m 7^2^37 003^13 3^2 • SGTH S C S -T H O M S O N M54HC76 M74HC76 S G S-THOMSON T-*t£-07-07 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR ■ HIGH SPEED fMAX = 60 MHz TYP. at Vc c = 5V ■ LOW POWER DISSIPATION lc c = 2 pJK (MAX.) at 25°C ■ OUTPUT DRIVE CAPABILITY


    OCR Scan     		PDF M54HC76 M74HC76 54/74LS76 M54HC76 M74HC76 M54/74HC76 G031fll7 74hc76

    TC74HC76

    Abstract: 74LS76 IC TC74HC76AP
    Text: TC74HC76AP/AF D U A L J - K F L I P - F L O P W IT H P R E S E T A N D C L E A R T h e T C 7 4 H C 7 6 A is a h ig h speed C M O S J - K F L IP FLO P fa b ric a te d w ith s ilic o n g a te C 2M O S tech n o lo g y. It ach ieve s the h ig h speed o p era tio n


    OCR Scan     		PDF TC74HC76AP/AF HC-207 HC-208 TC74HC76 74LS76 IC TC74HC76AP