7C340 Search Results

74151 waveform

Abstract: CY7C340 5128LC 7C340 programming 7C340 CY7C341B CY7C342B CY7C344 CY7C346 FLASH370
Contextual Info: 7c340: 12-13-90 Revision: October 19, 1995 7C340 EPLD Family Multiple Array Matrix HighĆDensity EPLDs called expander product terms. These exĆ Ċ VHDL simulation ViewSimt Ċ Available on PC and Sun platforms panders are used and shared by the macroĆ

7C34098

Abstract: LAH 50-P
Contextual Info: High Performance 2 5 6 K X 16 CMOS SRAM •■ I I AS7C4098 AS 7C34098 256KX16 CMOS SRAM • O rg a n izatio n : 2 6 2 ,1 4 4 w o rd s X 16 bits • H ig h sp eed - 1 2 / 1 5 / 2 0 / 2 5 ns ad d ress access tim e - 5 / 5 / 6 / 7 n s o u tp u t en ab le access tim e

AS7C31026

Abstract: AS7C34098 AS7C3513 AS7C4098 7c34098-12
Contextual Info: AS7C4098 7C34098 5V/3.3V 256Kx16 CMOS SRAM Features • Easy memory expansion with CE, OE inputs • TTL- and CMOS-compatible, three-state I/ • 44-pin JEDEC standard packages - 400 mil SOJ - 400 mil TSOP II • Center power and ground pins for low noise

7C34098-20

Abstract: AS7C34098 AS7C4098
Contextual Info: High Performance 256Kx16 CMOS SRAM AS7C4098 7C34098 256K×16 CMOS SRAM Preliminary information Features • Organization: 262,144 words × 16 bits • High speed - 15/20/25/35 ns address access time - 8/10/12/15 ns output enable access time • Low power consumption

Contextual Info: AS7C4-098 AS7C34-Ü98 ll i g l i P erform an ce 2 5 6 k x 16 CMOS SRAM 256KX16 CMOS' SRAM Prelim inary inform ation Features • O r g a n iz a tio n : 2 6 2 , 1 4 4 w o r d s X 16 b its E asy m e m o r y e x p a n s io n w i t h CE, O E in p u ts • H ig h s p e e d

Contextual Info: H ! y lì i’i ri \ S 7 < 4 !11*W A / S 6 K * : !• < M U S s !‘ s.; n î i 1>h ]•,/, ! ii i M i » !■ li. Features • O rg a n iz a tio n : 2 6 2 ,1 4 4 w o r d s x 16 b its • H ig h sp e e d • 4 4 - p in JEDEC sta n d a rd packages - 4 0 0 m il SOJ

7c4096a

Abstract: 7C4096 4096A
Contextual Info: A S 7C 4096 A S 7C 34096 5V/3.3V 512K x8 CMOS SRAM Features • O ig a n iz a tb n : 5 2 4 ,2 8 8 w o iris x 8 b i s • H igh gpeed - 1 2 / 1 5 / 2 0 / 2 5 n sa d c h ess access tim e - 5 / 5 / 6 / 7 n s o u tp u t en ab ie access tim e • lo w pow e r consum p t b n

Contextual Info: 7C340 EPLD Family 0 CYPRESS Multiple Array Matrix High-Density EPLDs — VHDL simulation ViewSim Features • Erasable, user-configurable CMOS EPLDs capable o f implementing highdensity custom logic functions • 0.8-micron double-metal CMOS EPROM technology (CY7C34X)

es 3880 fm

Abstract: BBS 8500 manufacturer code rohm AS7C34096 AS7C4096 t9140
Contextual Info: H ig h P e rf o rm a n ce AS7C 4096 A S7 C 34 09 6 5 1 2Kx8 CMOS SRAM A 5 l 2 K x 8 CMOS SRAM Preliminary information Features • Organization: 524,288 w ords x 8 bits • High speed - 1 2 /1 5 /2 0 /2 5 ns address access time - 6 / 7 / 8 / 9 ns output enable access time

7C4096

Abstract: AS7C34096 AS7C4096 5hbs AA344
Contextual Info: H igh Perform ance S12KX8 CMOS SRAM AS7C4096 A S7C 34096 1 5 1 2 K X 8 C M O S SR A M P relim inary inform ation SRAM Features • O rg a n iz a tio n : 5 2 4 ,2 8 8 w o rd s x 8 bits • H ig h sp e ed Easy m e m o ry e x p a n s io n w ith CE, OE in p u ts

Contextual Info: H igh Perform ance 512K X8 CMOS SRAM n II AS7C4096 A S7C 34096 5 1 2 K X 8 C M O S SR A M Preliminary information 1 E asy m e m o r y e x p a n s io n w i t h CE, O E i n p u ts Logic block diagram Pin arrangement SRAM Features • Organization: 524,288 words x 8 bits

Contextual Info: H igh P e r fo r m a n c e •■ AS7C4096 7C34096 A 512KX8 H CM O S SRAM 5 I 2 K X 8 C M O S SR A M Features • O rgan ization : 5 2 4 ,2 8 8 w o rd s x 8 bits • 3 6 -p in JEDEC stan dard pack ages • H igh speed - 4 0 0 m il T SO P II - 5 / S / 6 / 7 n s o u tp u t enable access tim e

AS7C34096-25JC

Contextual Info: AS7C4096 7C34096 5V/3.3V 512Kx8 CMOS SRAM Features • Organization: 524,288 w ords x 8 bits • High speed - 1 2 /1 5 /2 0 /2 5 ns address access time - 5 / 5 / 6 / 7 ns output enable access time • Low power consumption - Active: 990 m W max 20 ns cycle, 5V

Contextual Info: AS7C4098 7C34098 5Y/3.3Y 256Kxl6 CMOS SRAM Features • Organization: 262,144 words x 16 bits • Available in 3.3Y 7C34098 and 5Y (7C34098) versions • High speed - 10/12/15/20/25 ns address access time - 4/4/5/5/6/7 ns output enable access time

Contextual Info: Features • O rganization: 5 2 4 ,2 8 8 w o rd s x 8 bits • H igh speed - 1 2/1 S /2 0 /2 S ns address access tim e - 5 / 5 / 6 / 7 ns o u tp u t enable access tim e • l o w p o w er consum ption - Active: 990 m W m ax 20 ns cycle, 5V - Standby: 5 5 m W m ax (CMOS inputs)

212S

Abstract: BBS 8500 AS7C34098 AS7C4098 256KX16
Contextual Info: H ig h P e rfo rm a n c e A 256KXI6 C M O S SRAM A S7C 4098 A 7C34098 2 5 6 K X 1 6 C M O S SRAM Preliminary information Features • O rganization: 2 6 2 ,1 4 4 w o rd s x 16 bits • H ig h speed * Easy m em o ry exp a n sio n w ith CE, OE in pu ts - 1 5 / 2 0 / 2 5 / 3 5 ns address access tim e

7c4096-15

Abstract: AS7C34096 AS7C4096 BT105 IA171 AS7C4096-20JI 304 IR
Contextual Info: H ig h P e r f o r m a n c e « 512K X 8 C M O S SRAM II A S7C 4096 A S7C 34096 S I2 K X 8 CMOS SRAM • O rganization: 524,2 8 8 w o rd s x 8 bits • H igh speed - 1 2 / 1 5 /2 0 / 2 5 ns address access tim e - 5 / 5 / 6 / 7 ns o u tp u t enable access tim e

7C340

Abstract: rc 74151 IC 7400 SERIES book
Contextual Info: 7C340 EPLD Family CYPRESS SEMICONDUCTOR Multiple Array Matrix High-Density EPLDs — VHDL simulation ViewSim • Erasable, user-configurable CMOS EPLDs capable o f implementing highdensity custom logic functions — Available on PC and Sun platforms • 0.8-micron double-metal CMOS

Contextual Info: H i g h Pe rf o rm a n c e A S7C4096 A S7 C 34 096 512Kx8 CMOS SRAM A 5 1 2 K x 8 CMOS SRAM Preliminary information Features Easy memory expansion with CE, OE inputs TTL-compatible, three-state I/O 36-pin JEDEC standard package - 400 mil SOJ Center power and ground pins for low noise

7C340

Contextual Info: AT&T Advance Data Sheet January 1992 7C340 Microelectronics High-Speed CMOS 1 Mbit 128K x 8 SRAM Synchronous, Pipelined Architecture TTL Compatible Common I/O Features • High Speed — 10 ns maximuim access times ■ Registered addresses, data I/O, and control inputs

M140 Blue Laser Diode

Abstract: 12 volt electronic ballast for fluorescent light ledinta0350c425 philips xitanium 150W 1-10V XI040C070V056CNJ1 M140 laser diode t5 94v-0 tv philips
Contextual Info: Lighting Electronics Atlas A Full Line Catalog of LED Drivers, LED Modules, Ballasts and Lighting Controls 2014-2015 Contents Philips Advance LED Drivers Page 1-1 Philips LED Modules Page 2-1 Philips Advance Electronic Fluorescent Ballasts Page 3-1 Philips Advance Electronic Fluorescent Controllable Ballasts

datasheet CI 556

Abstract: AS7C34096 AS7C4096
Contextual Info: High Performance 512Kx8 CMOS SRAM AS7C4096 7C34096 512K×8 CMOS SRAM Preliminary information Features • Organization: 524,288 words × 8 bits • High speed - 12/15/20/25 ns address access time - 6/7/8/9 ns output enable access time • Low power consumption

epm5032dc

Abstract: 5130Q 5128A 74151 waveform 7C340 epld 342B rc 74151
Contextual Info: 7C340 EPLD Family •= CYPRESS Multiple Array Matrix High-Density EPLDs Features — VHDL sim ulation ViewSim M • Erasable, user-configurable CMOS EPLDs capable o f implementing highdensity custom logic functions — Available on PC and Sun platforms