7C602 Search Results

CYM6002K

Abstract: CY7C605 Cy7C601 AD31J 1RL0
Contextual Info: PR ELIM INARY CYM6002K CYPRESS SEMICONDUCTOR SPARCore Dual-CPU Module Features * Complete SPARC® Dual-CPU mod­ ule, including cache — TWo CY7C601 Integer Units IU — Two 7C602 Floating-Point Units (FPU) — Two CY7C605 Cache Controller and Memory M anagement Units

Contextual Info: Data Sheet February 1992 ATT7C157 m A T& T Microelectronics High-Speed CMOS Cache SRAM 256 Kbit 16K x 16 RISC-Based, Self-Timed, Latched Data I/O Features High speed — 15 ns maximum access time TTL compatible inputs and outputs Easy interface with SPARC' RISC architecture

CY7C601

Contextual Info: " ^ ^ 5 jF CY7C604A _ - _ - . - - - • - Cache Controller and Memory Management Unit CYPRESS — SEMICONDUCTOR Features • Fully conforms to the SPARC Reference Memory M anagement Unit M M U Architecture • Hardware table walk Description

ci 7495

Abstract: capacitor 107 16k 7C602 ATT7C157M-20 att cache
Contextual Info: HAR . ja;* Data Sheet February 1992 ATT7C157 m A T& T M icroelectronics High-Speed CMOS Cache SRAM 256 Kbit 16K x 16 RISC-Based, Self-Timed, Latched Data I/O Features High speed — 15 ns maximum access time TTL compatible inputs and outputs Easy interface with SPARC* RISC architecture

Cy7C601

Abstract: D6336 7C605
Contextual Info: CY7C605A r ^ p p rc c SEMICONDUCTOR Features • M ultiprocessing support • Pin-compatible with CY7C604A • Cache coherency protocol modeled af­ ter IEEE Futurebus • Separate virtual and physical cache tag memories — Each cache tag memory holds 2048

CY7C611

Contextual Info: CY7C611A CYPRESS SEMICONDUCTOR Features • SPARC processor optimized for em­ bedded control applications 32-Bit RISC Controller 136 32-bit registers — Eight overlapping windows o f 24 registers each — Dividing registers into seperate register banks allows fast context

7C602

Abstract: CY7C601
Contextual Info: 7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to CY7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • FullcompliancewithANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision

cy7c611

Abstract: CY7C602A asi cypress CY7C157A CY7C611A 38R1
Contextual Info: CY7C611A CYPRESS SEMICONDUCTOR Features • SPARC CD processor optimized for em­ bedded control applications • Reduced Instruction Set Computer RISC architecture — Simple format instructions — M ost instructions execute in a single cycle • Very high performance

JTAG MIPS

Abstract: Cy7C601 cy7c602 6001K 7C601 CY7C604
Contextual Info: r PRELIM INARY CYPRESS SEMICONDUCTOR CYM6001K = SPARCore CPU Module Features • Available at 2 5 ,33, and 40 MHz Functional Description • Complete SPARC® CPU solution, includingcache • Each SPARCore module features: — SPARC integer and floating-point

CY7C601

Abstract: cccv
Contextual Info: CY7C601A r ^ y p p r c c • — 32-Bit RISC Processor SEMICONDUCTOR — R egisters can be u sed a s e ight w in­ dows o f 24 registers each for low pro ced u re overhead Features • Reduced In stru c tio n Set C om puter R ISC A rchitecture — Sim ple fo rm at in stru ctio n s

Contextual Info: Dats Sheet January 1992 ATT7C157 - ATo.T - — M lo il Microelectronics High-Speed CMOS Cache SRAM 256 Kbit 16K x 16 RISC-Based, Self-Timed, Latched Data I/O Features • High-speed— 15 ns maximum access time ■ TTL compatible inputs and outputs ■ Advanced CMOS technology

CY7C601

Contextual Info: CYPRESS SEMICONDUCTOR 4LE » a s a ^ b L S - \2 .- 5 CYPRESS SEMICONDUCTOR Direct interface to CY7C601 integer unit Dircct interface to CY7C157 Caciie Storage Unit CSU Full compliance with ANSI/IEEE-754 standard for binary floating-point arithm etic Supports single and double precision

Cy7C601

Abstract: STD-745-1985 cy7c601a
Contextual Info: 7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to CY7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • Full compliance with ANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision

CY7C157A

Contextual Info: CY7C611A CYPRESS SEMICONDUCTOR Features • SPARC processor optimized for em ­ bedded control applications 32-Bit RISC Controller — Privileged instructions • 136 32-bit registers — Eight overlapping windows o f 24 registers each • Artificial intelligence support