8000002C Search Results

Contextual Info: 32 BIT MICROPROCESSOR FEATURES H Pipelined superscalar micro-architecture Central Processing Unit H W orkspace cache 32 bit Integer Unit H Programmable memory interface 7 Stage Pipeline H 4 Gbyte physical address space 64 bit Floating Point Unit H 16 Kbyte instruction and data cache

ic t805

Abstract: IMS T805-F20E inmos transputer inmos transputer T225 T425 T800 t225 Inmos t805 IMS T805-G20E MEMAD11
Contextual Info: SGS-THOMSON IMS T805E •HI 32-bit floating-point transputer - Extended temperature EATURES 32 bit architecture 50 ns internal cycle time 20 MIPS peak instruction rate 2.8 Mflops (peak) instruction rate Pin compatible with IMS T800 Floating Point Unit Debugging support

T9000

Abstract: STC104 IMST900-F20S IMST9000 inmos T9000 IMS processor inmos transputer reference manual
Contextual Info: IMS T9000 32 BIT MICROPROCESSOR FEATURES H Pipelined superscalar micro-architecture Central Processing Unit H Workspace cache 32 bit Integer Unit H Programmable memory interface 7 Stage Pipeline H 4 Gbyte physical address space 64 bit Floating Point Unit

MN103S

Abstract: LIN source code MATSUSHITA PANASONIC printer motor message display on LED pic MN10300 MN103S00 PC-9800 PT103
Contextual Info: MICROCOMPUTER MN10300 MN10300 Series C Source Code Debugger User’s Manual Pub.No.13130-022E PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. Sun, Sun OS, SPARC station2, and OpenWindows are registered trademarks of Sun Microsystems, Inc. USA .

T9000

Abstract: STC104 STC104s
Contextual Info: 32 BIT MICROPROCESSOR FEATURES H Pipelined superscalar micro-architecture Central Processing Unit H Workspace cache 32 bit Integer Unit H Programmable memory interface 7 Stage Pipeline H 4 Gbyte physical address space 64 bit Floating Point Unit H 16 Kbyte instruction and data cache

ST20450X40S

Abstract: A2531 60F5 enhanced ST20 manual st20 ST20 TOOLSET ST20 manual ST20 Embedded Toolset Reference Manual ST20450 ST20C4
Contextual Info: ST20450  32 BIT MICROPROCESSOR ENGINEERING DATA FEATURES • Enhanced 32-bit CPU • 0 to 40 MHz processor clock • 32 MIPS at 40 MHz • fast integer/bit operations ■ System Services 32-bit Processor 16 Kbytes on-chip SRAM • 160 Mbytes/s maximum bandwidth

T425

Abstract: T400 T414 T800 T805 inmos transputer T425 T800 transputer IMST425
Contextual Info: IMS T425 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 Debugging support 4 Kbytes on-chip static RAM System Services 100 Mbytes/sec sustained data rate to internal

T400 600

Abstract: IMS T414
Contextual Info: Low cost 32-bit transputer FEATURES • 32 bit architecture ■ 50 ns internal cycle time ■ 20 MHz only ■ 20 MIPS peak instruction rate ■ 10 MIPS sustained instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 ■ 2 Kbytes on-chip static RAM

IS07816-3

Abstract: 3se2 ST20 32bit ST20 TOOLSET transport demultiplexer set top box block diagram Hughes Microelectronics LS 5208 pinout ST20 Embedded Toolset 3XXXC
Contextual Info: SGS-THOMSON _D a@nniKM@ran@i_ ST20-TP1 PROGRAMMABLE TRANSPORT IC FOR DSS APPLICATIONS FEATURES • Enhanced 32-bit VL-RISC CPU • 0 to 40 MHz processor clock • fast integer/bit operations • very high code density ■ 8 Kbytes on-chip SRAM

IS07816-3

Abstract: LPC 248 microcontroller ST20-TP2 st20c2 DVB-C tuner 27mhz remote control transmitter circuit express card DVB LS 5208 pinout ST20 Embedded Toolset ST20 TOOLSET
Contextual Info: w# SGS -THOMSON ^7# MD g[M I[L[I(mi[M)R!]D(gS CTon TDO ST20-TP2 PROGRAMMABLE TRANSPORT 1C FOR DVB APPLICATIONS FEATURES • Enhanced 32-bit VL-RISC CPU 0 to 40 MHz processor clock fast integer/bit operations very high code density ■ 8 Kbytes on-chip SRAM

AD T805

Abstract: B50R MEMAD11 T805 IMS T805-F25S IMST805 transputer Inmos t805 inmos transputer T225 inmos transputer T425
Contextual Info: 32-bit floating-point transputer FEATURES • 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ 3.6 Mflops (peak) instruction rate ■ ■ Pin compatible with IMS T800, IMS T425, IMS T400 and IMS T414 Debugging support

Inmos t805

Abstract: IMS T805-F20E T425 T800 IMST800 21-F5 REAL32
Contextual Info: IMS T805E 32-bit floating-point transputer – Extended temperature FEATURES APPLICATIONS Scientific and mathematical applications High speed multi processor systems High performance graphics processing – HUD/HDD displays Supercomputers Workstations and workstation clusters

CQ 2AF1

Abstract: IMST425 IMS T400 Inmos T222
Contextual Info: 32-bit transputer FEATURES • 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 100 Mbytes/sec sustained data rate to internal

inmos T414

Abstract: inmos T400 12u-1919-g19 25f5 T400 600 inmos transputer T425 T400 clock T800 transputer AD T805 IMS T414
Contextual Info: IMS T400 Low cost 32-bit transputer FEATURES H 32 bit architecture H 50 ns internal cycle time H 20 MHz only H 20 MIPS peak instruction rate H 10 MIPS sustained instruction rate H Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 H 2 Kbytes on-chip static RAM

SPB-492

Abstract: dvb-c demultiplexer dvb-c transport Stream demultiplex APT 619 ap ST20TP2 BUT17
Contextual Info: ST20-TP2  PROGRAMMABLE TRANSPORT IC FOR DVB APPLICATIONS PRELIMINARY DATA FEATURES • Enhanced 32-bit VL-RISC CPU • 0 to 40 MHz processor clock • fast integer/bit operations • very high code density ■ 8 Kbytes on-chip SRAM • 160 Mbytes/s maximum bandwidth

STI5500

Abstract: STi55 STi5500 st20 ST20 TOOLSET ST20C2 set top box block diagram LS 2027 Final Audio video rgb splitter amplifier schematic ST20 twin decoder A215
Contextual Info: STi5500 SET TOP BOX BACKEND DECODER WITH INTEGRATED HOST PROCESSOR PRELIMINARY DATA FEATURES • Enhanced 32-bit VL-RISC CPU - 50 MHz clock • fast integer/bit operation and very high code density ■ High performance memory/cache subsystem • 2 Kbytes Instruction cache, 2K bytes SRAM,

ST20TP2BX50S

Abstract: ST20-TP2 ST20C2 27mhz remote control IC made in china ST20 TOOLSET LS 5208 pinout ST20 ISO7816-3 Conditional access module 72TRN-273
Contextual Info: ST20-TP2  PROGRAMMABLE TRANSPORT IC FOR DVB APPLICATIONS FEATURES • Enhanced 32-bit VL-RISC CPU 0 to 50 MHz processor clock fast integer/bit operations very high code density ■ 8 Kbytes on-chip SRAM 200 Mbytes/s maximum bandwidth ■ Programmable memory interface

ST20 TOOLSET

Abstract: LS 5208 pinout st20 ST20 Embedded Toolset ST20-TP1 ISO7816-3 L6605 STV0117
Contextual Info: ST20-TP1  PROGRAMMABLE TRANSPORT IC FOR DSS APPLICATIONS FEATURES • Enhanced 32-bit VL-RISC CPU • 0 to 40 MHz processor clock • fast integer/bit operations • very high code density ■ 8 Kbytes on-chip SRAM • 160 Mbytes/s maximum bandwidth ■ Programmable memory interface

VIPER 17H

Abstract: VIPER 27h 82c568 82C621A 486 system bus Viper 15 82C576 82C578 bios programmer 1F3H
Contextual Info: OPTi Inc. OPTi 888 Tasman Drive Milpitas, CA 95035 408 486-8000 Fax: (408) 486-8001 Application Note (OPTi Confidential) Product Name: Viper Xpress+ Chipset Title: BIOS Programming Guide Date: January 16, 1997 Scope Discussion This document outlines the recommended procedure for programming the internal registers of the Viper Xpress+ Chipset.

Inmos t805

Abstract: IMS T805-G25S IMS T805-F25S IMS T800 T400 T414 T425 T800 T805 inmos T414
Contextual Info: IMS T805 32-bit floating-point transputer FEATURES Floating Point Unit 32 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate 3.6 Mflops (peak) instruction rate Pin compatible with IMS T800, IMS T425, IMS T400 and IMS T414 Debugging support

dvb-c transport Stream demultiplex

Contextual Info: rrz ^ 7 / SGS -THOMSON OJgTOffleS ffi ST20-TP2 PROGRAMMABLE TRANSPORT 1C FOR DVB APPLICATIONS FEATURES • Enhanced 32-bit VL-RISC CPU 0 to 50 MHz processor clock fast integer/bit operations very high code density ■ 8 Kbytes on-chip SRAM 200 Mbytes/s maximum bandwidth