80960KA Search Results

80960KA

Abstract: 80960KB 80960MC 270775
Contextual Info: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions

FLS 441

Abstract: 27960K2-25 27960KX SS31 aos trace code
Contextual Info: irrte1 27960KX BURST ACCESS 1M 128K x 8 CHMOS EPROM • Synchronous 4-Byte Data Burst Access ■ Simple Interface to the 80960KA/KB ■ Asynch Microcontroller Reset Function ~ " e*ur"s to Known state with Hi9h z Outputs a . .« * « .- * ■ CHMOS’ lll-E for High Performance and

Contextual Info: 85C960 1-MICRON CHMOS 80960 K-SERIES BUS CONTROL juPLD • Burst Logic, Ready Control, and Address Decode Support for 80960 KA/KB Embedded Controllers in Single Chip ■ Operates with 80960KA/KB at 20 MHz and 25 MHz ■ Ice = 50 mA Max. ■ UV Erasable CerDIP or OTPTM

LAD19

Abstract: G101032 290192 ICE960
Contextual Info: IN T E L CORP in te i U P /P R P H L S 44E D a 4 fl2 b l7 S D IO IQ O S T E iIT L l; T = ^ ? - I 7 ~ s t 80960KA EMBEDDED 32-BIT PROCESSOR • High-Perform ance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 M IPS4 Sustained Execution at

i960 KA/KB Programmers Reference Manual

Abstract: i960 KA/KB Reference Manual 80960JA 80960JD 80960JT 80960KA 80960KB 80960KX Intel 80960kb programmers reference
Contextual Info: Upgrading System Designs from i960 Kx to the i960 Jx Processors Upgrading System Designs from i960® Kx to the i960 Jx Processors Technical Note October 1998 1.0 Introduction Intel designed the 80960Jx products to be an easy upgrade choice from the existing 80960KA/KB

i960 Cx Instruction Set Quick Reference

Abstract: 80960KA 80960KB 80960MC TA80960 270775
Contextual Info: in te i, 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

270775

Contextual Info: in te i 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

MIPS 32-bit bus architecture

Abstract: cache architecture for MIPS 1 32-BIT
Contextual Info: intei 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instruc­

ali m 3329

Abstract: PROCESSOR ALI 3329 ALI M 3329 d1 ali 3329 ali 3329 b 3329 ali LAD31 canon pinout cartridge printer ali m 3328 canon printer power supply
Contextual Info: [ P l ^ D P y t S T [pß?G in te i 82961KA PAGE PRINTER CONTROLLER High Integration i960 Page Printer Controller^1 — Direct Interface to 32-bit 80960KA or KB 2) Embedded Processors Direct Non-Impact Printer Video Interface — Automatic DMA Burst DRAM Access

80960KB Programmer Reference manual

Abstract: 80960KA 80960KB pqfp132 PGA-132
Contextual Info: Intel 80960KA/KB Specification Update August 2004 Notice: The Intel® 80960KA/KB may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.

i960 Cx Instruction Set Quick Reference

Contextual Info: in t e i, 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

80960KA

Abstract: 80960KB 80960MC TA80960KA pga 132 packaging
Contextual Info: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions

PAL Decoder 16L8

Abstract: intel microcontroller 8096 8096 microcontroller features 27960K2-25 27960KX D-10 intel PLD
Contextual Info: i n t e J 27960KX BURST ACCESS 1M 128K x 8 CHMOS EPROM • Synchronous 4-Byte Data Burst Access ■ Simple Interface to the 80960KA/KB ■ High Performance Clock to Data Out — Zero Wait State Data-to-Data Burst — Supports 16, 20 and 25 MHz 80960KA/KB Devices

27960K2-25

Abstract: 27960KX D-10 intel PLD
Contextual Info: in te J ra n u s M u m 27960KX BURST ACCESS 1M 128K x 8 CHMOS EPROM • Synchronous 4-Byte Data Burst Access ■ Simple Interface to the 80960KA/KB ■ High Performance Clock to Data Out — Zero Wait State Data-to-Data Burst — Supports 16, 20 and 25 MHz

85C960

Abstract: D85C960-20 231369 d85c960-25 Erasable Programmable Logic Device 610 LSC5
Contextual Info: in te i 85C960 1-MICRON CHMOS 80960 K-SERIES BUS CONTROL juPLD Burst Logic, Ready Control, and Address Decode Support for 80960 KA/KB Embedded Controllers In Single Chip Operates with 80960KA/KB at 16 MHz, 20 MHz, and 25 MHz UV Erasable CerDIP or O T P tm

TA80960kb

Abstract: TA80960KA 80960KB Programmer Reference manual 80960KA 80960KB A80960KA A80960KB NG80960KA TA80960
Contextual Info: Intel 80960KA/KB Specification Update June 2000 Notice: The Intel® 80960KA/KB may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.

Contextual Info: 5hE D • M fl2bl7S INTEL 011M07S CORP 402 ■ IT L 1 U P/PR PH LS 80960KA EMBEDDED 32-BIT PROCESSOR ■ Built-In Interrupt Controller — 32 Priority Levels 256 Vectors — 3.4 jlis Latency @ 25 MHz _ Easy to Use, High Bandwidth 32-Bit Bus — 66.7 Mbytes/s Burst

29023

Contextual Info: A E W Ä N K g i O M lP iO Ä Ä T D ^ 27960KX BURST ACCESS 1M 128K x 8 EPROM • Synchronous 4-Byte Data Burst Access ■ Simple Interface to the 80960KA/KB ■ High Performance Clock to Data Out Time — Zero Wait State Data to Data Burst — Supports 16, 20 and 25 MHz

Contextual Info: intei 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

231369

Abstract: intel 27213 canon pinout cartridge printer 82961KA
Contextual Info: [p R ® y T r a n in te i 82961KA PAGE PRINTER CONTROLLER High Integration i960® Page Printer Controller^1 — Direct Interface to 32-bit 80960KA or KB 2) Embedded Processors Direct Non-Impact Printer Video Interface — Automatic DMA Burst DRAM Access

5223 eprom

Abstract: 29023
Contextual Info: m g y iM O N M v 27960KX BURST ACCESS 1M 128K x 8 CHMOS EPROM • Synchronous 4-Byte Data Burst Access ■ Simple Interface to the 80960KA/KB ■ High Performance Clock to Data Out — Zero Walt State Data-to-Data Burst — Supports 16, 20 and 25 MHz 80960KA/KB Devices

Contextual Info: t n t e T 27960KX BURST ACCESS 1M 128K x 8 CHMOS EPROM Synchronous 4-Byte Data Burst Access • Asynch Microcontroller Reset Function — Returns to Known State with High Z Outputs Simple Interface to the 80960KA/KB High Performance Clock to Data Out — Zero Walt State Data-to-Data Burst

82961KA

Abstract: canon pinout cartridge printer video board "canon " printer
Contextual Info: P e ® y T [FiraEWQQ in t e i 82961KA PAGE PRINTER CONTROLLER High Integration i960® Page Printer Controlled1 — Direct Interface to 32-bit 80960KA or KB<2) Embedded Processors Direct Non-Impact Printer Video Interface — Automatic DMA Burst DRAM Access

TA80960kb

Abstract: KD80960KB-16 v929 TA80960KB-25 TA80960KB16 TA80960KB25 intel 8276 V928 LA809 TA80960KA
Contextual Info: 80960KA/KB SPECIFICATION UPDATE Release Date: July, 1996 Order Number: 272851-001 The 80960KA/KB may contain design defects or errors known as errata. Characterized errata that may cause the 80960KA/KB’s behavior to deviate from published specifications are