82355 Search Results

doorbell circuit application

Abstract: MCC63
Contextual Info: irrtef [P fô ilO M O M V 82355 6.0 FIFO/DATA ALIGNER to the system. The BMIC will relinquish the bus to the system if the CFGFF bit in the channel’s corre­ sponding Configuration register is set to a 1. 6.1 FIFO/Data Aligner The BMIC uses two identical FIFOs, one per transfer

Contextual Info: 82355 9.0 DETAILED PIN DESCRIPTION 9.1 EISA Interface Signals Pin Name Description START# I/O TRI-STATED EISA CYCLE START STROBE The START# signal provides timing control at the start of a cycle. During EISA master mode, the BMIC drives this signal low after LA <31:2> and M /IO become valid and negates

XC96

Abstract: XC87 82355 XC8F XC89 EISA chip set XC90
Contextual Info: 82355 13.0 BMIC PN AND PACKAGE INFORMATION 13.1 Signal Overview Name = Pin Name, Type = I— Input, O—Output, OC— Open Collector, B— Both Input and Output, BC— Both and Open Collector, Pin = Pin Location Name Type Pin Description EISA BUS INTERFACE SIGNALS

82355

Contextual Info: 82355 The 82355 Bus Master Interface Controller BMIC is a highly integrated Bus Master designed for use in 32-Bit EISA Bus Master expansion board designs and supports all of the enhancements defined in the EISA specifications required for EISA bus master ap­

82358

Abstract: XC96 8251 intel microcontroller architecture F245B intel 82358 INTERFACING OF 8272 WITH 8086 EISA chip set 82355 ta 8271 hq intel 82355
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed fo r use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 M b ytes/S ec Maximum Data

Contextual Info: inter P B IIU IIM IIIN IÄ IB V 82355 11.0 D.C. SPECIFICATIONS NOTICE: This data sheet contains preliminary infor­ mation on new products in production. The specifica­ tions are subject to change without notice. 11.1 Maximum Ratings* * WARNING: Stressing the device beyond the “Absolute

XC90

Abstract: intel 82358
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data

XC90

Contextual Info: in tj 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three Interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data

C80h-C9Fh

Contextual Info: 82355 3.0 FUNCTIONAL OVERVIEW The follow ing is a brief discussion of the functional blocks and features of the 82355. The EISA inter­ face, Transfer Buffer interface, F IF O /D a ta Aligner, and Local interface each have a corresponding de­ tailed section later in this data sheet.

82355

Abstract: 29025
Contextual Info: IF^IlDMDRyw intei 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three Interfaces (EISA, Local CPU, and Transfer Buffer) Supports Automatic Handling of Complete EISA Bus Master Protocol

Contextual Info: infel. 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three Interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data

MM3007

Abstract: MM3002 MM3003 82355 25CC 2N2904 725M MM2005 MM3001 MM3005
Contextual Info: MOTOROLA SC -CXSTRS/R F> 6367254 TL MOTOROLA SC XSTRS/R DE | t,3fci72SM 0 G Û 2 3 5 S F 96D 82355 D MAXIMUM RATINGS Symbol Value Unit Colfector-Emitter Voltage v CEO 20 Vdc Collector-Base Voltage VCBO 25 Vdc Emitter-Base Voftage Ve b o 4.0 Vdc Collector Current— Continuous

82355

Contextual Info: PBiyMOMABSV 82355 10.0 BASIC FUNCTION TIMING DIAGRAMS EISA INTERFACE S IG N A LS M REQ# — I MAKjif S T AR T # CMD# m / io , w / r • . . . . . . . . - • — :- ^

t8760

Contextual Info: m 82355 y ß M M v 12.0 A.C. S P E C IF IC A T IO N S 12.1 A.C. C h aracteristics T ab le s The A.C. specifications given in the following tables consist of output delays/float times and input setup and hold times. T ca SE = 0°C to 70°C, VCC = 5V ± 5 % , T AMB|ENT = 0°C to 55°C

Contextual Info: MOT OR OL A SC -CXSTRS/R 6367254 F> Tb MOTOROLA SC DE | CXSTRS/R F b3t,72SM 96D 0GÛ235S 82355 MAXIMUM RATINGS Symbol Value Unit Collector-Emitter Voltage v CEO 20 Vdc Collector-Base Voltage V CBO 25 Vdc Emitter-Base Voltage v EBO 4.0 Vdc Collector C u rren t— Continuous

82055

Abstract: pico electronics transformers ct 60 transistor 82350 82577 82305 82385 6404
Contextual Info: Audio Transformers: 2 Ohm to 135K Ohm; 75Hz to 30KHz; 1.5 watt at 1KHz SURFACE MOUNT PICO surface mount units utilize materials and methods to withstand extreme temperatures of vapor phase, I.R., and other reflow procedures without degradation of electrical or mechanical characteristics.

Contextual Info: BROOKTREE CORP b3E B • 1^455^5 DDQ7G3T Interface Specification IS-210.15 SMDS C o n tro l and R e a sse m b ly F o r m a tte r Part # UGA-210 M arch, 1993 Brooktree Brooktree Corporation 9950 Barnes Canyon Road San Diego, CA 92121 USA 6 1 9 -4 5 2 -7 5 8 0

MCH3307

Abstract: SBS004 ENN8235 2171A
Contextual Info: CPH5838 Ordering number : ENN8235 CPH5838 MOSFET : P-Channel Silicon MOSFET SBD : Schottky Barrier Diode General-Purpose Switching Device Applications Features • • DC / DC converters. Composite type with a P-Channel Sillicon MOSFET MCH3307 and a Schottky Barrier Diode (SBS004)

rsm 2814

Contextual Info: 1.0 Product Description - The Bt8209 and Bt8210 Switched Multimegabit Data Service SMDS Control and Reassembly Formatters (SCARF) provide a single-access SMDS service ter­ mination for connectionless data, “datagram,” transfer according to Bellcore TRTSV-000772 and TR-TSV-000773. Customer Premise Equipment (CPE) and

82055

Abstract: TH 82420 82440
Contextual Info: \ * so •“TiSbod* *• P5KS <M-* - j a r S B « s -— \ \ PICO PART numkr ' \ 82003 S E R IE S 82000 T 0601'9*1 H “ - Tr 170 4 Mi I BOOttO B2» -G 3 ►- • -4 r70l« Ml l • 82075 300 Ct 12 Ct 3 82085 82090 300 ct 300 ct 300 ct 50 Ct 150 ct 125

sei smd resistors

Abstract: sei smd 1206 resistors RMC 0805 1K
Contextual Info: SEI Electronics Kits and Thick Film Chip Resistors Visit SEI ElectronicsÕ Website at www.seielect.com Chip Resistor Kits Stock No. Mfr.Õs Type Package Size Tol. % Values Kit Qty. EACH Stock No. Mfr.Õs Type Package Size Tol. % Values Kit Qty. EACH 823-0100

intel 82350

Abstract: intel 82352 82351 eisa intel 82357 intel 82358 82359 82350DT EISA Chip Set Design Guide 2LF 1418 82350DT
Contextual Info: in te i 82358DT EISA Bus Controller • Supports 82350 and 82350DT Chip Set Based Systems — Mode Selectable for Either 82350 or 82350DT Based Systems — Mode Defaults to 82350 Based Systems ■ Socket Compatible with the 82358 EISA Bus Controller ■ Provides EISA/ISA Bus Cycle

23/QSCH-5374

Contextual Info: Audio Transformers: 2 Ohm to 135K Ohm; 75Hz to 30KHz; 1.5 watt at 1KHz SURFACE MOUNT PICO surface mount units utilize materials and methods to withstand extreme temperatures of vapor phase, I.R., and other reflow procedures without degradation of electrical or mechanical characteristics.

Contextual Info: Extract from the online catalog ST 2,5-TWIN-DIO/R-L Order No.: 3036521 The illustration shows version ST 2,5-TWIN-DIO/L-R Component terminal block, Connection type: Spring-cage connection,