82S2 Search Results

Contextual Info: BIPOLAR M E M O R Y PRODUCTS £ 2 -£Z lo 2304-BIT BIPOLAR RAM 25 6x 9 DESCRIPTION (P°C to 7 5 °C) s p e c ify N 8 2S 210F o r N and fo r th e m ilita ry te m p e ra tu re ra n g e ( - 5 5 °C to + 1 2 5 °C) s p e c ify S 82S210F. T h e 82S 210 d a ta in p u ts a n d o u tp u ts are

Contextual Info: Signetics Memories - Bipolar Ram C O N N E C TIO N D IA G R A M 82S208 - 2048 Bit Bipolar Ram 256 x 8 G E N E R A L DE SC R IPTIO N The 82S208 data inputs and o u tp u ts are com m o n (com m on I/O ) w ith separate o u tp u t disable (OD) line th a t allow s ease

82S230

Abstract: 82S231 N82S230N N82S231N Signetics TTL 82S130 S82S23
Contextual Info: Signetics Memories - Bipolar Rorn 82S230, 82S231 - 2048 Bit Bipolar Rom 512 x 4 C O N N E C T IO N D IA G R A M Both 82S230 and 82S231 devices are available in the commercial and m ilitary temperature ranges. For the commercial temperature range (0 °C to +75°C) specify

74S189

Abstract: 74818 s189 82S25
Contextual Info: BIPOLAR M E M O R Y DIVISION M AY 1982 64-BIT BIPOLAR SCRATCH PAD MEMORY 16x4 82S25 (O.C.), 3101A (O.C.), 54/74S189 (T.S.) ABSOLUTE MAXIMUM RATINGS RATIN G PARAMETER1 Vcc S u p p ly vo ltage V in Input voltage +7 Vdc + 5 .5 Vdc Vdc O u tp u t vo ltage V oh

N82S123F

Abstract: N82S123N N82S23F 82S123 programming N82S23N 82S123 SIGNETICS prom signetics 82S123 n82s123 82S23
Contextual Info: Signetics Mem ories - Bipolar Prom s Programming Signetics P R O M S CONNECTION DIAGRAM PROM programming is available through ITT Gemini for further details please contact your local sales office. 82S23/N82S123 PROM 256 Bit Bipolar GENERAL DESCRIPTION The 82S23 and 82S123 are field programmable, which

Contextual Info: Signetics 82S212/82S212-40 2304-Bit TTL Bipolar RAM 256 x 9 Product Specification Military Bipolar Memory Products PIN CONFIGURATION DESCRIPTION FEATURES The organization of the 82S212-40 allows byte wide storage of data, including parity. Where parity is not required, the ninth bit

Contextual Info: 82S25-F.N • 3101 A -F.N • 54/74S89-F.N • 54/74S189-F.N DESCRIPTION APPLICATIONS T his fa m ily o f R ead/W rite R andom A ccess M em ories is ideal fo r use in scra tch pad and h igh-speed b u ffe r m em ory ap p lic a tio n s . • Scratch pad memory

rom 512x8

Abstract: chip 8205 82S214 8205 A 82S215
Contextual Info: signotics 2048-BIT BIPOLAR ROM 256x8 ROM 4096-BIT BIPOLAR ROM (512x8 ROM) 8204 8205 82S 214) 82S215 DIGITAL 8000 SERIES TTL/MEMORY DESCRIPTION PIN CONFIGURATION T h e 8 2 0 4 / 8 2 S 2 1 4 a n d 8 2 0 5 / 8 2 S 2 1 5 are S c h o ttk y - c la m p e d R e ad

82S200

Abstract: 82S100 RESISTOR variable 82S201 signetics 82s100
Contextual Info: B2S2A0 T.S.Ì/82S201 ¿P.C. 82S200-I.N • 82S201-I.N DESCRIPTION The 82S200 (tri-state outputs) and the 82S201 (open c o lle c to r outputs) are B ip o la r P rogram m able Lo gic A rrays, c o n ta in in g 48 p ro d u c t term s (AND terms), and 8 sum term s

82S208

Abstract: 82S2 33um
Contextual Info: 82S208-F • 82S210-F.N DESCRIPTION The 82S208 and 82S210 data inputs and o u tp u ts are com m on com m on I/O w ith separate output disable (OD) line tha t a l­ low s ease of re a d /w rite operations using a common bus. The a d dress inputs have a latch feature con­

IC 82S123

Abstract: N82S23N n82s123n
Contextual Info: Philips C o m p o n e n ts -S ig n e tic s D o c u m e n t N o . 8 5 3 -0 1 54 ECN N o. 86487 Date o f Is s u e N ove m b e r 11, 1986 S ta tu s P roduct S pecification 82S23 82S123 256-bit TTL bipolar PROM M em ory P ro du cts PIN CONFIGURATIONS DESCRIPTION

82S230

Abstract: 82S231
Contextual Info: 82S230-F.N • 82S231-F.N The 82S230 and 82S231 in c lu d e o n -c h ip d e coding and 1 ch ip enable in p u t fo r ease of m em ory expansion. T h ey feature eith er open c o lle c to r or tri-s ta te o u tp u ts fo r o p ti­ m ization of w ord expansion in bused org a n ­

82S2708

Abstract: N82S2708F N82S2708 S82S2708
Contextual Info: S ig n e tic s Memories - Bipolar Proms- 82S2708 - 8192 Bit Field Programmable Bipolar Prom CONNECTION DIAGRAM GENERAL DESCRIPTION The 82S2708 is field programmable, which means that custom patterns are immediately available by follow ing the fusing procedure given in this data sheet. The standard

26 SIGNETICS

Abstract: 32X2 32X8 82S21 74181 pin configuration
Contextual Info: MAY 1982 BIPOLAR MEMORY DIVISION 64-BIT BIPOLAR WRITE-WHILE-READ RAM 32 x 2 TIMING DIAGRAMS 2-10 (C on td ) Signetics 82S21 (O.C.) BIPOLAR MEMORY DIVISION MAY 1982 64-BIT BIPOLAR WRITE-WHILE-READ RAM ( 3 2 x 2 ) 82S21 (O .C .) TYPICAL APPLICATION BASIC 8-B IT FULLY BUFFERED A C C U M ULATO R

bipolar rom 256*4

Abstract: prom 256x4 bit signetics 1016 82S226 82S229
Contextual Info: sggnotiBS 1024-BIT BIPOLAR READ ONLY MEMORY 256x4 ROM FEBRUARY 1975 82S226 82S229 DIGITAL 8000 SERIES TTL/MEMORY DESCRIPTION PIN CONFIGURATION Th e 82S226 (Open Collector Outputs) and the 82S229 (Tri-State Outputs) are Bipolar 1024-Bit Read O n ly Mem­

82s100

Abstract: 82S200
Contextual Info: APPLICATIONS* • • • • • • • • • • • • • The 82S200 and 82S201 are fu lly TTL com­ patible, and include chip enable control for expansion of input variables, and output inhibit. They feature either open collector or tri-state outputs for ease of expansion of

N82S123AN

Abstract: 82s123 philips 82S123A N82S123AA 82S23A N82S23A N82S23AD N82S123A 82S123 82S23
Contextual Info: Philips Semiconductors Product specification 256-bit TTL bipolar PROM 32 x 8 DESCRIPTION 82S23A/82S123A FEATURES The 82S23A and 82S123A are field programmable, which means that custom patterns are immediately available by following the Signetics Generic I fusing procedure. The 82S23A

signetics 82S123

Abstract: signetics 82s23 SIGNETICS* fusing procedure 82S123 82s123 philips N82S123N 82s23 philips 82S23 N82S123 N82S23
Contextual Info: Philips Semiconductors Product specification 256-bit TTL bipolar PROM 32 x 8 DESCRIPTION 82S23/82S123 FEATURES The 82S23 and 82S123 are field programmable, which means that custom patterns are immediately available by following the Signetics Generic I fusing procedure. The 82S23

82S123n

Abstract: a4nj 2s123 82s23 IC 82S123
Contextual Info: Philips Components-Signetics ECN No. 86487 Date of Issue N ove m b e r 11, 1986 82S23 82S123 Status P roduct S pecification 256-bit TTL bipolar PROM Document No. 8 5 3 -0 1 54 M em ory P roducts DESCRIPTION FEATURES The 82S 23 and 8 2S 123 are field program m able, w hich m eans that

82S23B

Abstract: 82s123b "Bipolar PROM" Signetics Generic I fusing procedure
Contextual Info: 82S23B, 82S123B Signetics 256-Bit TTL Bipolar PROM Military Bipolar Memory Products Product Specification DESCRIPTION FEATURES APPLICATIONS The 82S23B and 82S123B are field-programmable, which means that custom patterns are immediately available by following the Signetics Generic I fusing

prom 2708

Abstract: S82S2708F 82S2708 S82S2708 1024x8 PROM p-iris control
Contextual Info: MAY « 8 2 BIPOLAR M EM O RY DIVISION 8 192-BIT BIPOLAR PROM 1024 X 8 82S2708 (T.S.) PIN CONFIGURATION DESCRIPTION FEATURES The 82S2708 Is fie ld program m able, w hich means th a t custom patterns are im m ediate­ ly available by fo llo w in g the fu sin g p roce ­

82S210

Abstract: N82S210 N82S210F S82S210 S82S210F
Contextual Info: MAY 1982 BIPOLAR MEMORY DIVISION 2304-BIT BIPOLAR RAM 256 X 9 DESCRIPTION The 82S210 data inputs and outputs are common (common I/O) w ith separate out­ put disable (OD) line that allows ease of read/write operations using a common bus. 82S210 (T.S.) (0°C to 75 °C) specify 82S210F or N and

82S25

Abstract: N74S189N N3101A N74S189 N82S25 N82S25N S54S189 S82S25
Contextual Info: BIPOLAR MEMORY DIVISION MAY 1982 64-BIT BIPOLAR SCRATCH PAD MEMORY 16x4 82S25 (O.C.), 3101A (O.G.), 54/74S189 (T.S.) DESCRIPTION APPLICATIONS T h is fa m ily o f R ead/W rite R andom Access M em ories is ideal fo r use in scra tch pad and high-speed b u ffe r m em ory a pp licatio n s.

aj 312

Abstract: 82S226 82S229 N82S226N N82S229N
Contextual Info: S ig n e tic s M em ories - Bipolar Rom 82S226, 82S229 - 1024 Bit Bipolar Rom 256 x 4 C O N N E C T IO N D IA G R A M A .ΠG E N E R A L D E SC R IPTIO N The 82S226 and 82S229 include on-chip decoding and 2 c h ip enable inpu ts fo r ease o f m em o ry expansion. The y _