8B/10B ALIGN Search Results

Marvell fibre copper

Abstract: marvell alaska marvell IEEE
Contextual Info: Transceiver Solutions Alaska X 10GBASE-CX4 Transceiver 88X2088 PRODUCT OVERVIEW Dev. 4 PHY XGXS L0 L1 L2 L3 L0 L1 L2 L3 LASI Deserializer 8B/10B Decoder FIFO Dev. 3 PCS 8B/10B Encoder Serializer 8B/10B Encoder FIFO 8B/10B Decoder LASI MDC MDIO INTn Management

virtex-7

Abstract: Aurora LX240T virtex7 vhdl coding for error correction and detection xilinx virtex-7 Spartan-6 LXT LX240T-FF1156 kintex 7
Contextual Info: LogiCORE IP Aurora 8B/10B v8.1 DS797 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core supports the AMBA protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the

virtex-6 ML605 user guide

Abstract: virtex-7 sp605 verilog code 8 bit LFSR UG476 ARM v7 block diagram virtex7
Contextual Info: LogiCORE IP Aurora 8B/10B v7.1 DS797 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core supports the AMBA protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the

virtex-6 ML605 user guide

Abstract: UG353 vhdl code 8 bit LFSR ML605 UCF FILE virtex 5 fpga utilization simple 32 bit LFSR using verilog 65Gbps SP006 virtex-5 ML605 user guide aurora GTX
Contextual Info: LogiCORE IP Aurora 8B/10B v5.3 DS637 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex -5 LXT, SXT, FXT, and TXT

528-58

Abstract: A54SX16 A54SX16-2 AC135 VQ100 K28-1 pd6bc
Contextual Info: Application Note AC135 Implementing an 8b/10b Encoder/Decoder for Gigabit Ethernet in the Actel SX FPGA Family Introduction This application note describes how an Actel A54SX16 FPGA was used to implement an 8b/10b encoder/decoder function for a Gigabit Ethernet router.

xc3s50atq144

Abstract: xc3s50a-tq144 xc5vlx20t-ff323 XAPP1112 XAPP1122 vhdl ethernet spartan 3a 16 word 8 bit ram using vhdl K27 v6 K28-1
Contextual Info: Application Note: Virtex-5, Virtex-4, Virtex-II, Virtex-II Pro, Spartan-3, Spartan-3E, Spartan-3A/3A DSP R Parameterizable 8b/10b Decoder Author: Paula Vo XAPP1112 v1.1 November 10, 2008 Summary This application note describes a parameterizable 8b/10b Decoder, and is accompanied by a

CY7B923

Abstract: CY7B933 CY7C42X5 CY7C924ADX
Contextual Info: CY7C924ADX 200 MBaud HOTLink Transceiver Features • Second generation HOTLink® technology • Fibre Channel and ESCON® compliant 8B/10B encoder/decoder • 10 or 12 bit preencoded data path raw mode • 8 or 10 bit encoded data transport (using 8B/10B coding)

32C05

Abstract: CY7B923 CY7B933 CY7C42X5 CY7C924ADX CY7C924ADX-AI
Contextual Info: CY7C924ADX 200 MBaud HOTLink Transceiver Features • Second generation HOTLink® technology • Fibre Channel and ESCON® compliant 8B/10B encoder/decoder • 10 or 12 bit preencoded data path raw mode • 8 or 10 bit encoded data transport (using 8B/10B coding)

0D100

Abstract: pd6bc
Contextual Info: Appl i cat i o n N ot e Implementing an 8b/10b Encoder/Decoder for Gigabit Ethernet in the Actel SX FPGA Family Introduction This application note describes how an Actel A54SX16 FPGA was used to implement an 8b/10b encoder/decoder function for a Gigabit Ethernet router.

porte logique

Abstract: porte logique and TS83084G0 circuit logique Transistor 8c4 TS83084G TS81102G0 TS83102G0 TS8388B TSEV8388G
Contextual Info: MAIN FEATURES ! Programmable DMUX ratio : 1:4 : Data rate max = 1 Gsps, PD 8b/10b < 4.3 / 4.7 W (ECL 50Ω output) 1:8 : Data Rate max = 2GSPS, PD (8b/10b)< 6 / 6.9 W (ECL 50Ω output) 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX. ! Parallel output mode.

porte logique

Abstract: TS8387 b511 Current Output Temperature 81102G0 B511 transistor porte logique and CQFP68 TS81102G0 TS8388B TSEV83102G0F
Contextual Info: MAIN FEATURES § Programmable DMUX ratio : 1:4 : Data rate max = 1 Gsps, PD 8b/10b < 3.8 / 4.1 W (ECL 50Ω output) 1:8 : Data Rate max = 2GSPS, PD (8b/10b)< 5.0 / 5.7 W (ECL 50Ω output) 1:16 with 1 TS8388B and 2 DMUX. § Parallel output mode. § 8/10 bit.

Contextual Info: f PRELIMINARY CYPRESS C Y 7 C 92 4D X 200 MBaud HOTLink Transceiver Features Second generation HOTLink™ technology Fibre Channel and ESC O N com pliant 8B /10B encoder/decoder 10- or 12-bit pre-encoded data path raw m ode 8- o r 10-bit encoded data transport (using 8B/10B

2f 1001

Abstract: D1024A 11010
Contextual Info: 10. Data & Control Codes SGX52010-1.0 8B/10B Code This appendix provides information about the data and control codes for the Stratix GX device. Code Notation The 8B/10B data and control codes are referred to as Dx.y and Kx.y, respectively. The 8-bit byte H G F E D C B A, where H is the MSB and A

2f 1001

Abstract: AGX52004-1 D313 equivalent
Contextual Info: 4. Specifications and Additional Information AGX52004-1.0 8B/10B Code This section provides information about the data and control codes for Arria GX devices. Code Notation The 8B/10B data and control codes are referred to as Dx.y and Kx.y, respectively. The 8-bit byte – H G F E D C B A, where H is the most

TS81102G0FS

Abstract: TS81102G0 TS83102G0 TS83102G0B TS8388B Diode D25 N12 Diode D25 N6
Contextual Info: Main Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4 Data Rate Max = 750 Msps – PD 8b/10b < 4.3/4.7W (ECL 50Ω Output) – 1:8 Data Rate Max = 1.5 Gsps – PD (8b/10b) < 6/6.9W (ECL 50Ω Output) – 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX

Contextual Info: Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4: Data Rate Max = 1 Gsps – PD 8b/10b < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX

CQFP68

Abstract: TS81102G0 TS83102G0 TS83102G0B TS8388B TSEV8388G 0251C
Contextual Info: Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4: Data Rate Max = 750 Msps – PD 8b/10b < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 1.5 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX

Atmel 749

Abstract: 2-CQFP Atmel 122 Ai203-ceramic TS81102G0VTP TS83102G0 TS83102G0B TS8388B TS81102G0 TS81102G0CTP
Contextual Info: Main Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4 Data Rate Max = 1 Gsps – PD 8b/10b < 4.3/4.7 W (ECL 50 Ω Output) – 1:8 Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50 Ω Output) – 1:16 With 1 TS8388B or 1 TS83102G0 and 2 DMUX

TS83084G0

Abstract: CQFP68 TS81102G0 TS83102G0 TS8388B TSEV8388G
Contextual Info: Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4: Data Rate Max = 1 Gsps – PD 8b/10b < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX

AD9803

Abstract: AD9803JST
Contextual Info: a CCD Signal Processor for Electronic Cameras AD9803 Preliminary Technical Data PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PBLK PGACONT1-2 CLPOB AD9803 CLAMP 0–30dB 10 PGA CDS CCDIN MUX CLAMP DAC1 S/H ADC AUXCONT PGA 8B DAC 10B DAC REF CLAMP DAC2 8B DAC

atmel 022

Abstract: AT78C5081 sata
Contextual Info: Features • General – – – – – – – – Serial ATA Rev.1.0a Compliant Gen1 Physical Layer 150 MHz Frequency Synthesizer for ASIC Clock Generation Built-in Transmission PLL Circuits Parallel 10b interface Optional 20-bit Transmit Data Two 10-bit 8b/10b Encoded Characters

Contextual Info: Application Layer Transport Layer Physical Layer Data Link Layer Transmitter Block Tx Application Layer SYSREF optional SYNC~ Device Clock Data Framing Frame/Lane Alignment Character Generation Scrambler (Optional) 8b/10b Encoder Serializer Tx Driver High

CY7B923

Abstract: CY7C42X5 CY7C954ADX ASC CAPACITOR 29C04
Contextual Info: CY7C954ADX ATM HOTLink Transceiver Framer Deserializer Decoder 8B/10B HOTLink devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-topoint serial links. Some applications include interconnecting

49mhz remote control receiver circuit

Abstract: 49mhz transmitter and receiver
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Advance Product Information Gigabit Interconnect Chip VSC7211 Features • Deskewing of +/- 2 Bits Cable Skew at the Receiver Across Multiple Chips • ANSI X3T11 Compatible Fibre Channel Transceiver • 8B/10B Encoder/Decoder