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    8KX1 RAM Search Results

    8KX1 RAM Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MD2114A/BVA Rochester Electronics LLC STATIC RAM; 1K X 4 Visit Rochester Electronics LLC Buy
    27S13A/BEA Rochester Electronics LLC 27S13A - 2048-Bit (512X4) Bipolar RAM Visit Rochester Electronics LLC Buy
    CY7C09389V-9AXI Rochester Electronics CY7C09389 - 3.3 V 64 K X 18 Synchronous Dual-Port Static RAM, Industrial Temp Visit Rochester Electronics Buy
    CDP1824CD/B Rochester Electronics LLC CDP1824C - 32-Word x 8-Bit Static RAM Visit Rochester Electronics LLC Buy
    MC68A02CL Rochester Electronics LLC MC68A02 - Microprocessor With Clock and Oprtional RAM Visit Rochester Electronics LLC Buy

    8KX1 RAM Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    SECDED

    Abstract: sram 16k8 EP3SE50
    Text: 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.1 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640-bit memory logic array blocks


    Original     		PDF SIII51004-1 640-bit 144-Kbit M144K SECDED sram 16k8 EP3SE50

    dual port ram

    Abstract: EP2AGX260 A123 C789 EP2AGX125 EP2AGX190 EP2AGX45 EP2AGX65 shiftregister
    Text: 3. Memory Blocks in Arria II GX Devices AIIGX51003-2.0 Arria II GX memory blocks include 640-bit memory logic array blocks MLABs and 9-Kbit M9K blocks. You can configure each embedded memory block independently to be a single- or dual-port RAM, FIFO, ROM, or shift register with the Quartus ® II


    Original     		PDF AIIGX51003-2 640-bit dual port ram EP2AGX260 A123 C789 EP2AGX125 EP2AGX190 EP2AGX45 EP2AGX65 shiftregister

    SECDED

    Abstract: EP3SE50
    Text: 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.8 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640- in ROM mode only or 320-bit memory logic array blocks (MLABs),


    Original     		PDF SIII51004-1 320-bit 144-Kbit M144K SECDED EP3SE50

    8kx1 RAM

    Abstract: 8kx1
    Text: Application Note Axcelerator Family Memory Blocks I n tro du ct i on blocks in each device depends on the number of core tiles. For example, in an AX125 device with a single core tile, the number of available memory blocks is 4, while the AX500, with four core tiles, has 16 memory blocks. Note that the


    Original     		PDF AX125) AX2000) 128x36, 256x18, 512x9, 8kx1 RAM 8kx1

    8kx1 RAM

    Abstract: AX125 AX2000 AC164
    Text: Application Note AC164 Axcelerator Family Memory Blocks I n tro du ct i on blocks in each device depends on the number of core tiles. For example, in an AX125 device with a single core tile, the number of available memory blocks is 4, while the AX500, with four core tiles, has 16 memory blocks. Note that the


    Original     		PDF AC164 AX125 AX500, AX250 AX125) AX2000) 8kx1 RAM AX2000 AC164

    delta39k

    Abstract: No abstract text available
    Text: Delta39KTM and Quantum38KTM Single-Port Memory Introduction Channel and Cluster Memory The purpose of this application note is to provide instruction for all aspects of implementing synchronous/asynchronous Single-Port Random-Access-Memory SPRAM and Single-Port Read-Only-Memory (SPROM) in Delta39K and


    Original     		PDF Delta39KTM Quantum38KTM Delta39K Quantum38K

    Untitled

    Abstract: No abstract text available
    Text: CHAPTER 4 SUMMARY OF MENUS, COMMANDS, AND OPERATIONS MAIN MENU ICEBOX File Configuration! Help The Main Menu window of the emulator graphical user interface GUI is displayed after the GUI program is started. The following menu items can be accessed from this Main Menu:


    Original     		PDF ST96Z8X0300 Z86E02 Z86E03 Z86E04 Z86E06 Z86E08 Z86E30 Z86E31 Z86E33 Z86E34

    add round key for aes algorithm

    Abstract: verilog code for twiddle factor ROM C6316 fpga frame by vhdl examples LUT-based-64 verilog code for crossbar switch
    Text: Section I. Device Core This section provides a complete overview of all features relating to the Stratix III device family, which is the most architecturally advanced, high performance, low power FPGA in the market place. This section includes the following chapters:


    Original     		PDF

    logic diagram to setup adder and subtractor

    Abstract: DIN 5463 add round key for aes algorithm circuit diagram of inverting adder H.264 encoder verilog code for twiddle factor ROM vhdl code for complex multiplication and addition EP3SE50 1517-Pin VHDL codes of 16 point FFT radix-4
    Text: Section I. Device Core This section provides a complete overview of all features relating to the Stratix III device family, which is the most architecturally advanced, high performance, low power FPGA in the market place. This section includes the following chapters:


    Original     		PDF

    8kx1 RAM

    Abstract: 82C691 CY10 CY82C691 CY82C692 CY82C693 512k ADS22
    Text: ADVANCED INFORMATION Features Pentiumt hyperCachet Chipset System Controller D Supports synchronous or asynchronous PCI operation D Supports six banks of DRAM six RAS lines D D D Supports DRAM densities up to 16 Mb D Provides glueless (0 TTL) system solution with CY82C692 and


    Original     		PDF CY82C692 CY82C693 208pin 8Kx21 8kx1 RAM 82C691 CY10 CY82C691 CY82C693 512k ADS22

    vhdl code SECDED

    Abstract: EP3SE50 dual_port
    Text: Internal Memory RAM and ROM User Guide UG-01068-1.0 November 2009 Introduction Altera provides various internal memory (RAM and ROM) features to address the memory requirements of today's system-on-a-programmable-chip (SOPC) designs. You can use the following methods to create the memory with the features you desire:


    Original     		PDF UG-01068-1 vhdl code SECDED EP3SE50 dual_port

    vhdl code for phase frequency detector for FPGA

    Abstract: carry select adder vhdl pin configuration for half adder vhdl code for complex multiplication and addition vhdl code of carry save adder 32 bit carry select adder in vhdl circuit diagram of half adder GPON block diagram logic diagram to setup adder and subtractor verilog code for barrel shifter
    Text: Section I. Device Core This section provides a complete overview of all features relating to the Arria II GX device family, the industry’s first cost-optimized 40 nm FPGA family. This section includes the following chapters: • Chapter 1, Arria II GX Device Family Overview


    Original     		PDF

    2500AD

    Abstract: Z86C15 Z86K15 Intel 486 computer schematic zilog CROSS
    Text: Z86K15 ICEBOX Emulator Electrical Safeguards WARNING! Follow the precautions listed below to avoid permanent damage to the emulator. I. Always use a grounding strap to prevent damage resulting from electrostatic discharge ESD . II. Power-Up Precautions.


    Original     		PDF Z86K15 down65 UM010001-0301 ST97KEY0100 2500AD Z86C15 Intel 486 computer schematic zilog CROSS

    XC6SL

    Abstract: SPARTAN 6 Configuration SPARTAN-6 DS512 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18
    Text: Block Memory Generator v3.3 DS512 September 16, 2009 Product Specification Introduction • The Xilinx LogiCORE IP Block Memory Generator core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs.


    Original     		PDF DS512 XC6SL SPARTAN 6 Configuration SPARTAN-6 RAMB36 RAMB18 RAMB18SDP hamming decoder vhdl code spartan 3 multiprocessor 2Kx18

    CY39200V

    Abstract: No abstract text available
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin


    Original     		PDF Delta39KTM NT208 51-85069-B 388-Lead MG388 256-Ball BB256/MB256 1-85108-A CY39200V

    82C691

    Abstract: CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C694 cy82 C691H
    Text: PRELIMINARY CY82C691 Pentiumt hyperCachet Chipset System Controller Features DProvides power management support DSupports six banks of DRAM six RAS DIntegrated 8Kx21 tag (direct mapped or DSupports DRAM densities up to 16 Mb DUp to 768 MB main memory Dvariable drive on DRAM address and


    Original     		PDF CY82C691 8Kx21 82C691 CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C694 cy82 C691H

    CY39100V484-125BBI

    Abstract: "Single-Port RAM" delta39k
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Multiple I/O standards supported — LVCMOS, LVTTL, 3.3V PCI, SSTL2 I-II , SSTL3 (I-II), HSTL (I-IV), and GTL+ •Compatible with NOBL™, ZBT™, and QDR™ SRAMs •Programmable slew rate control on each I/O pin


    Original     		PDF Delta39KTM CY39100V484-125BBI "Single-Port RAM" delta39k

    NT208

    Abstract: 1kx8 rom 250NTC
    Text: Delta39K ISR™ CPLD Family PRELIMINARY CPLDs at FPGA Densities™ •Carry-chain logic for fast and efficient arithmetic operations •Multiple I/O standards supported — LVCMOS 3.3/3.0/2.5/1.8V , LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+


    Original     		PDF Delta39KTM 250-MHz NT208 1kx8 rom 250NTC

    Untitled

    Abstract: No abstract text available
    Text: KM 71 8V787 1 2 8 K x 1 8 S y n c h r o n o u s SR A M Document Title 1 2 8Kx1 8-Bi t S y n c h r o n o u s B u r s t S R A M , 3. 3V P o w e r D a t a s h e e t s for 1 0 0 T Q F P Revision History Rev. No. H Istorv Draft Date R e m ar k Rev. 0.0 Initial draft


    OCR Scan     		PDF 8V787 1997x 128Kx18 100-TQFP-1420A

    8kx1 RAM

    Abstract: 125 va pt dty 8kx1
    Text: 3.3V 12 8K 8Kx1 6-BIT CACHE-TAG SRAM For 3.3V P r o c e s s o r s FEATURES: H IG H M A T C H o u tp u t is g e n e ra te d w h e n th e s e tw o g ro u p s of d a ta a re th e s a m e fo r a g iven a d d re ss. T h is h ig h -sp e e d M A T C H sig n a l is a v a ila b le as soon a s 10 n s a fte r the a d d re ss


    OCR Scan     		PDF IDT71 200mV 8kx1 RAM 125 va pt dty 8kx1

    44 wa3

    Abstract: 8kx1
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 128KB and 256KB Secondary Cache Fast Static RAM Modules MCM32A32 MCM32A64 With Tag for 486 Processor Based Systems The MCM32A32 and MCM32A64 are two products in Motorola’s asynchro­ nous secondary cache module family for the 486 processor. The modules are


    OCR Scan     		PDF 128KB 256KB MCM32A32 MCM32A64 32A32 32A64 MCM32A32£ MCM32A64Í 44 wa3 8kx1

    8kx1 RAM

    Abstract: SN74BCT216012 D3512 SN74ACT2160 SN74BCT2160-12
    Text: SN74BCT2160 8K x 4 2-WAY CACHE ADDRESS COMPARATOR/TAG RAM SCHS011 - D3512, JUNE 1990- REVISED MARCH 1992 Fast Address to Match Time. . . 12 ns Max IO Upgrade of the SN74ACT2160 FM PACKAGE TOP VIEW o • 't CO OJ 1- o < < < < < < Q 2-Way Architecture Significantly Improves


    OCR Scan     		PDF SN74BCT2160 SCHS011 D3512, SN74ACT2160 FM032 R-PLCC-J32 8kx1 RAM SN74BCT216012 D3512 SN74BCT2160-12

    Untitled

    Abstract: No abstract text available
    Text: CYPRESS PRELIMINARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Provides control for the cache, system memory, and the PCI bus PCI Bus Rev. 2.1 compliant Supports 3V Pentium™ , AMD K5, and Cyrix 6x86 M1 CPUs Support for WB or W T L1 cache


    OCR Scan     		PDF CY82C691 8Kx21

    8kx1 RAM

    Abstract: 82c pci isa tagram
    Text: Pentium hyperCache™ Chipset System Controller Featu res Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support fo r standard 72-bit-wide DRAM banks • Provides control fo rth e cache, system memory, and the


    OCR Scan     		PDF 8Kx21 72-bit-wide 8kx1 RAM 82c pci isa tagram