8KX2 Search Results

Contextual Info: ENERGY METER: Embedded DSP AFE Embedded dspConverters AD73560 AD73560 8/9/01 40 80 2:11 PM AD73360 AD73360 ADSP2185L ADSP2185L 52 52 19 19 16.7 to 26 16.7 to 26 8Kx24 16Kx24 Ed Grokulsky 8Kx16 16Kx16 Rev-4 12/03/00 YES YES YES YES YES YES A A 119 BGA 119 BGA

Contextual Info: - D ata R A M / ROM bit 6k X 2 3 - - 8kx23 W ork RAM (bit) LCD segm ent Model No. I k x 8 /2 5 6 x 4 480 SM3503 1 5 1 2 X 8 /2 5 6 X 4 480 SM3504 < 5 1 2 X 8 /2 5 6 X 4 384 SM3507 2 k X 8 /2 5 6 X 4 540 SM3509 8 k X 8 /2 5 6 X 4 540 SM3512 MICROCOMPUTERS

CYL7

Abstract: Cyrix 6x86 MX CPU 82c691
Contextual Info: PRELIMINARY CY82C691 Pentium hyperCache™ Chipset System Controller •Provides power management support through SMM APM Compliant •Integrated 8Kx21 tag (direct mapped or two-way set associative) •Support for cache sizes up to 1 MB •Supports mixed standard page-mode

HE2V

Contextual Info: MOTOROLA SEM ICO NDUCTO R TECHNICAL DATA MCM56824A Product Preview DSPRAM 8Kx24 Bit Fast Static RAM T ha M C M 5 6 8 2 4 A is a 1 9 6 ,6 0 8 b it s ta tic ra n d o m a c c e s s m e m o ry o rg a n iz e d as 8 ,192 w o rd s o f 2 4 bits, fa b ric a te d u sing M o to ro la 's h ig h -p e rfo rm a n c e s ilic o n -g a te

32Kx16

Abstract: AD73322 rom 8kx16 8kx16 870110
Contextual Info: COMMUNICATIONS: DSP SOLUTIONS MODEL MODEL Option On Chip Generic A/D or Codec On Chip DSP MIPS CYLCE TIME nsec CLK IN MHZ PROGRAM RAM ROM DATA RAM DMA PORTS HOST PORT TEMPERATURE Vcc RANGE +3.3V 0>70 -25/85 Smallest Package # Pins 2Kx24 PROGRAM RAM FLASH 8Kx24

line buffer

Contextual Info: Application Specific Fast Static RAMs Latched/Asynchronous Address MCM56824A MCM62995A MCM67A518 MCM67A618 MCM67A618A 8Kx24 . 4-3 16Kx16 . 4-72 32Kx18 . 4-92 64Kx18 . 4-103

MC56824

Abstract: MCM56824-25 MCM56824 MC56824-35 MCM56824FN35 56824/D
Contextual Info: MOTOROLA SEM ICO NDUCTOR TECHNICAL DATA MCM56824 Product Preview DSPRAM 8Kx24 Bit Fast Static RAM The MCM56824 is a 196,608 bit static random access memory organized as 8,192 words of 24 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology. The device integrates an 8Kx24 SRAM oore with multiple chip

82C691

Abstract: CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C694 cy82 C691H
Contextual Info: PRELIMINARY CY82C691 Pentiumt hyperCachet Chipset System Controller Features DProvides power management support DSupports six banks of DRAM six RAS DIntegrated 8Kx21 tag (direct mapped or DSupports DRAM densities up to 16 Mb DUp to 768 MB main memory Dvariable drive on DRAM address and

MC68B21CP

Abstract: xcm916x1cth16 transistor marking code 12W SOT-23 sg379 MC68B54P XC68HC805P18CDW mc68b50cp MC2830 NE555N CHN NE555N
Contextual Info: SG379/D REV 7 Semiconductor Products Sector NORTH AMERICA SALES AND DISTRIBUTION PRICE LIST THIS BOOK IS IN COMPUTER SORT PRODUCT CLASSIFICATION – Please see General Information Section 1.3 EFFECTIVE DATE: JANUARY 10, 1998 General Information 1 Cross References

2561b

Abstract: CPU 314 IFM 8kx1 RAM cy17 ALI chipset fast page mode dram controller CY2254ASC-2 CY27C010 CY82C691 CY82C693
Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support for standard 72-bit-wide DRAM banks Supports non-symmetrical DRAM banks

723653

Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide

DSP56200

Abstract: adaptive FILTER implementation in c language fixed point goertzel GOERTZEL ALGORITHM SOURCE CODE DSP56K IIR FILTER implementation in c language GOERTZEL ALGORITHM SOURCE CODE for dtmf in c iir adaptive Filter using of lms algorithm Motorola DSP56200 LMS adaptive filter
Contextual Info: SECTION 11 ADDITIONAL SUPPORT Motorola ola DSP Audio: Codec Routines: DTMF Routines: Fast Fourier Transforms: Filters: Floating-Point Routines: Functions: Lattice Filters: Matrix Operations: Reed-Solomon Encoder: Sorting Routines: Speech: Standard I/O Equates:

Contextual Info: CYPRESS PRELIMINARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Provides control for the cache, system memory, and the PCI bus PCI Bus Rev. 2.1 compliant Supports 3V Pentium™ , AMD K5, and Cyrix 6x86 M1 CPUs Support for WB or W T L1 cache

xc3s500e fg320

Abstract: intel strataflash j3d SPARTAN 3E STARTER BOARD transistor tt 2222 pin configuration 500K variable resistor eeprom programmer schematic winbond AT45DB AT49 jtag cable Schematic XC3S500E spartan 3a
Contextual Info: Spartan-3E FPGA Family: Complete Data Sheet R DS312 April 18, 2008 Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312-1 v3.7 April 18, 2008 DS312-3 (v3.7) April 18, 2008 • • • •

DSP56300 finite impulse response

Abstract: an1782 DSP56303 C120 DSP56307 FM4001 MC33269DT 32Kx24-bit
Contextual Info: MOTOROLA Order by AN1782/D Order Number Rev. 0 , 1/99 Semiconductor Application Note Contents Converting DSP56303 Designs to DSP56307 Designs by Iantha Scheiwe This document details the differences between the DSP56303 and the DSP56307 that must be considered when a system

IEC-297-3

Abstract: IEC297-3 dsp56001 architecture DSP56000 DSP56001 MC68000 PB12 "saturation arithmetic"
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 24-Bit General Purpose Digital Signal Processor Order this document by DSP5600I/D DSP56001 Pin Grid Array PGA Available in an 88 pin ceramic through-hole package. Ceramic Quad Flat Pack (CQFP) The DSP56001 is a member of Motorola’s family of

8kx1 RAM

Abstract: 82c pci isa tagram
Contextual Info: Pentium hyperCache™ Chipset System Controller Featu res Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support fo r standard 72-bit-wide DRAM banks • Provides control fo rth e cache, system memory, and the

6226m

Abstract: dsp56374 dsp56371
Contextual Info: Freescale Semiconductor Data Sheet: Technical Data DSP56371 Rev. 4, 10/2005 DSP56371 Data Sheet WMSG MAD Division 1 Introduction The DSP56371 is a high density CMOS device with 5.0-volt compatible inputs and outputs. NOTE This document contains information on a new product.

4JX24SPP

Contextual Info: Multipair Extension Cable Common extension wire types are made up into standard multipair cables. Each conductor is covered with a polyvinyl jacket, nominal 0.38 mm 0.015" thick, and the pairs are individually twisted. Clear Mylar tape is then wrapped around the bundle of twisted

xc3s500e vq100

Contextual Info: 1 Spartan-3E FPGA Family Data Sheet DS312 July 19, 2013 Product Specification Module 1: Introduction and Ordering Information Module 3: DC and Switching Characteristics DS312 v4.1 July 19, 2013 DS312 (v4.1) July 19, 2013 • Introduction • • Features

7136a

Abstract: 6523m 1103u 2581a 8903M 4539A 3801u DSP56000 2666A DSP56374
Contextual Info: Freescale Semiconductor Technical Data DSP56371 Rev. 3, 1/2005 Table of Contents 1 Section Introduction Page 1 Introduction . 1 The DSP56371 is a high density CMOS device with 5.0-volt compatible inputs and outputs. 2 DSP56371 Overview. 1

verilog code for dual port ram with axi interface

Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
Contextual Info: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories

AC97

Abstract: DSP56300 DSP56366 IEC958
Contextual Info: Freescale Semiconductor, Inc. Advance Information DSP56366/D Rev. 1.6, 01/2004 Freescale Semiconductor, Inc. 24-Bit Audio Digital Signal Processor Topic Page Overview . i Signal/Connection Descriptions .1-1

APR39

Abstract: 4Kx24-bit an1782 C120 C121 DSP56303 DSP56307 FM4001 DSP56300 finite impulse response
Contextual Info: Order by AN1782/D Order Number Rev. 0 , 1/99 Converting DSP56303 Designs to DSP56307 Designs This document details the differences between the DSP56303 and the DSP56307 that must be considered when a system based on the DSP56303 is redesigned for use on the