90C157 Search Results

Contextual Info: LHE D MATRA M H s • SöböMSb GDÜSMEb Töl BllinHS H lftiilll January 1991 7 ^ ~ z 3 ~ / 3 DATA SHEET_ 90C1 57 1 6 , 3 8 4 x 1 6 S T A T IC R /W R A M FEATURES ■ ■ ■ ■ DATA IN AND DATA OUT LATCHES SELF-TIMED WRITE

90c61

Abstract: Trap floating point
Contextual Info: 4 CIE D MATRA M H S • SñbñMSb 00023^^ _ F p B A f C lllììlilll I w T B W 414 «M M H S _ " 3 8 January 1991 90C601 DATA SHEET_ 32-BIT RISC PROCESSOR FEATURES ■ REDUCED INSTRUCTION SET COMPUTER RISC ARCHITECTURE - SIMPLE FORMAT INSTRUCTIONS

F4T5

Abstract: selectronic MAD45 csta 020 26
Contextual Info: M l WHS electronic June 1992 90C600 HI-REL DATA SHEET The 90C600 chip-set is a 32-bit custom CMOS implementation of the SPARCT architecture. The 90C600 CPU includes the 90C601 Integer Unit IU , the 90C602 Floating-Point Unit (FPU), the 90C604 Cache controller and MMU (CMU),