95XXXX Search Results

XC9536XL

Abstract: XAPP114 XAPP427 XC9500XL XC9536 Pb-Free Marking Codes XC9536XL VQFP XC9536XL-10VQ64C VQG44 XC9536XL-10VQ44
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.7 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

Contextual Info: XC9536XV High-performance CPLD R DS053 v2.4 May 27, 2003 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)

PC44

Abstract: VQ44 XAPP361 XC9500XV XC9572XV
Contextual Info: XC9572XV High-performance CPLD R DS052 v2.5 August 21, 2003 5 Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins)

XC9572XL

Abstract: xc9572xl pin configuration XC9572XL-5VQ44C XAPP114 XAPP427 XC9500XL XC9572 XC9572XL-10 XC9572XL-5 XC9572XL-7
Contextual Info: XC9572XL High Performance CPLD R DS057 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

PC44

Abstract: XAPP361 XC9500XV XC9536XL XC9536XV B1.66 20E2
Contextual Info: XC9536XV High-performance CPLD R DS053 v2.5 August 21, 2003 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)

952703BFLF

Abstract: ICS952703 sis741 952703BF
Contextual Info: ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Programmable Timing Control Hub for K7TM System Recommended Application: SiS741 style chipset with 964 South Bridge. Features/Benefits: • Selectable synchronous/asynchronous AGP/PCI frequency

xilinx MARKING CODE

Contextual Info: XC9536XV High-performance CPLD R DS053 v2.7 January 16, 2006 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint package - 44-pin VQFP (34 user I/O pins) Optimized for high-performance 2.5V systems

Contextual Info: Product Obsolete/Under Obsolescence XC9536XV High-performance CPLD R DS053 v3.0 June 25, 2007 1 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices

marking code f4 3 pin

Contextual Info: XC9572XV High-performance CPLD R DS052 v2.6 April 15, 2005 5 Product Specification Features • • • • • • • • PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)

xc9572xl pin configuration

Abstract: XC9572XL XC9572XL-7VQ44I DS057 xc9572xl pin XC9572XL-10CS48C XAPP114 XC9500XL XC9572 XC9572XL-10
Contextual Info: XC9572XL High Performance CPLD R DS057 v1.4 August 21, 2003 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

XC95XX

Abstract: XAPP361 XC9500XV XC9536XL XC9536XV XCN07010 xilinx MARKING CODE XCN05020 mclp
Contextual Info: XC9536XV High-performance CPLD R DS053 v3.0 June 25, 2007 1 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to

7400 series CMOS Logic ICs

Contextual Info: ICS952702 Integrated Circuit Systems, Inc. Programmable Timing Control Hub for K7TM System Recommended Application: SiS746/746FX style chipset Output Features: • 1 - Pair of differential open drain CPU outputs • 1 - Single-ended open drain CPU output •

sbx 1620

Abstract: L 7206 SBE160 95500-01 L7206 6363G1 261G2 LH-SBE320-SL 75XXX-XX 75500-01
Contextual Info: W i r v e r b i n d e n S i e Inhalt Allgemeines 3-5 SB Stecker SB 50, SB 175, SB 350 6-7 SBX Stecker SBX 175, SBX 350 8-9 SBE Stecker SBE 80, SBE 160, SBE 320 DIN-Stecker 14 - 15 säurebeständige DIN-Stecker 16 - 17 Powerpole Pak 18 - 19 Powerpole 20 - 21

Contextual Info: Product Obsolete/Under Obsolescence XC9572XV High-performance CPLD R 5 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9572XV devices with equivalent XC9572XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to

XC9536XL

Abstract: 95xxxXL XC9536XL VQFP xc9536xl-5 XC9536XL-10VQ44 XAPP427 VQG44 XC9536XL-5PCG44C XC9500XL XC9536XL-7PC44C
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.9 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)

Contextual Info: XC9572XL High Performance CPLD R DS057 v1.5 July 15, 2004 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

VQG44

Abstract: XC9536XL-10VQ44I XC9536XL 84 PLCC pin configuration XAPP114 XAPP427 XC9500XL XC9536 xc9536 44 pin vqfp
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.6 September 15, 2004 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output

Contextual Info: ICS952703 Preliminary Product Preview Integrated Circuit Systems, Inc. Programmable Timing Control Hub for K7TM System Recommended Application: SiS741 style chipset with 964 South Bridge. Features/Benefits: • Selectable synchronous/asynchronous AGP/PCI frequency

xc9572xl pin configuration

Abstract: XC9572XL XC9572XL-7TQG100C XC9572XL-5VQG44C XAPP427 44 VQFP package 84 PLCC pin configuration XC9572XL-10TQ100C XC9572XL-7CSG48C XC9572XL-7VQ44I
Contextual Info: XC9572XL High Performance CPLD R DS057 v1.6 September 15, 2004 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output

xc9572xl pin configuration

Abstract: XC9572XL XC9572XL-10PCG44C XC9572XL-10CS48I XC9572XL-10VQG44C XC9572XL-7TQ100C XC9572XL-10PC44C xc9572xl-10PCG44C pin XC9572XL-7PCG44C XC9572XL-5TQG100C
Contextual Info: XC9572XL High Performance CPLD R DS057 v2.0 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins)

XAPP361

Abstract: XC9500XV XC9572XL XC9572XV XCN07010
Contextual Info: XC9572XV High-performance CPLD R 5 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9572XV devices with equivalent XC9572XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to

V18 marking

Abstract: XC9536XL-5VQ44C VQG44
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.8 March 22, 2006 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

Contextual Info: XC9536XL High Performance CPLD R DS058 v1.5 July 15, 2004 5 Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

Contextual Info: XC9572XV High-performance CPLD R DS052 v2.4 June 18, 2003 5 Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins)