CY7C132 Search Results

64KX32

Abstract: 7C13 CY7C1329
Contextual Info: fax id: 1080 1CY 7C13 29 CY7C1329 PRELIMINARY 64K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1329 is 3.3V 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

INTEL 80,82

Abstract: intel 80.82 intel 8082 INTEL 80-82 CY7C1325 ASYNCHRONOUS COUNTER
Contextual Info: CYPRESS CY7C1325 256K x 18 Synchronous 3.3V Cache RAM Features Functional Description • Supports 117-M Hz microprocessor cache systems with zero wait states • 256K by 18 common I/O • Fast ciock-to-output times — 7.5 ns 117-M Hz version • Two-bit wrap-around counter supporting either inter­

Contextual Info: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth

Contextual Info: fax id: 5201 CY7C132/CY7C136 CY7C142/CY7C146 W CYPRESS 2Kx8 Dual-Port Static RAM Features Functional Description True Dual-Ported memory cells which allow sim ulta­ neous reads of the same mem ory location 2K x 8 organization 0.65-micron CMOS for optimum speed/power

Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-raicron CMOS for optimum speed/power • BÜSŸ output flag on CY7C132/ CY7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY 7C136/CY7C142/

CY7C1325G

Abstract: CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI
Contextual Info: CY7C1325G PRELIMINARY 4-Mbit 256K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 256K X 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version)

CY7C1327B

Contextual Info: 327 CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

CY7C1327G

Abstract: CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI
Contextual Info: CY7C1327G PRELIMINARY 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times

7N19

Abstract: CY7C1316AV18 CY7C1318AV18 CY7C1320AV18
Contextual Info: CY7C1316AV18 CY7C1318AV18 CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at

CY7C1316BV18

Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
Contextual Info: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

A101

Abstract: CY7C1329G CY7C1329G-133AC CY7C1329G-166AC
Contextual Info: CY7C1329G 2-Mb 64K x 32 Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times counter for internal burst operation. All synchronous inputs are

CY7C132

Abstract: CY7C136 CY7C146
Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports

CY7C1328A

Abstract: GVT71256F18
Contextual Info: 327 CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 128K x 36/256K x 18 Synchronous-Pipelined Cache RAM Features • • • • • • • • • • • • • • • • • Fast access times: 3.5, 3.8, and 4.0 ns Fast clock speed: 166, 150, 133, and 117 MHz

Contextual Info: CY7C1327 256K X 18 Synchronous-Pipelined Cache RAM Features The CY7C1327 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V DDQ=2.5V. • Supports 1 0O-MHz bus for Pentium and PowerPC operations with zero wait states

CY7C1328G-200AXC

Abstract: CY7C1328G CY7C1328G-133AXC CY7C1328G-133AXI CY7C1328G-166AXC
Contextual Info: CY7C1328G 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18 common I/O architecture

CY7C1328G

Abstract: CY7C1328G-166AXC CY7C1328G-200AXC CY7C1328G-250AXC
Contextual Info: CY7C1328G PRELIMINARY 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18-bit common I/O architecture

CY7C1326H

Contextual Info: CY7C1326H 2-Mbit 128K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 128K x 18 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

Z1213

Abstract: CY7C132 CY7C136 CY7C146 zl12
Contextual Info: bSE » CYPRESS SEMICONDUCTOR SSÖ'lbbE 0 0 0 ^ 7 4 7 ISb I CYP CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM output enable OE . BUSY flags are pro­ vided on each port. In addition, an interrupt Functional Description Features

Contextual Info: CY7C1327G 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times

intel 8082

Abstract: intel 80.82 INTEL 80,82
Contextual Info: PRELIMINARY CY7C1325B 256K x 18 Synchronous 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 256K by 18 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wrap-around counter supporting either interleaved or linear burst sequence

Contextual Info: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1328G PRELIMINARY 4-Mbit 256K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 256K x 18-bit common I/O architecture

Contextual Info: CY7C1317V18 CY7C1319V18 CY7C1321V18 PRELIMINARY 18-Mb DDR -II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency

Contextual Info: CY7C1324H 2-Mbit 128K x 18 Flow-Through Sync SRAM Features • 128K x 18 common I/O • 3.3V core power supply • 3.3V/2.5V I/O supply • Fast clock-to-output times — 6.5 ns (133-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel