CY7C146 Search Results

Contextual Info: CY7C1460AV25 CY7C1462AV25 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: fax id: 5201 CY7C132/CY7C136 CY7C142/CY7C146 W CYPRESS 2Kx8 Dual-Port Static RAM Features Functional Description True Dual-Ported memory cells which allow sim ulta­ neous reads of the same mem ory location 2K x 8 organization 0.65-micron CMOS for optimum speed/power

Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM Features Functional Description • 0.8-raicron CMOS for optimum speed/power • BÜSŸ output flag on CY7C132/ CY7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY 7C136/CY7C142/

Contextual Info: CY7C146-55JC 1/3 IL08 * C-MOS 16K (2048 x 8)-BIT STATIC RAM R IN 47 A10 48 INT R OUT 49 BUSY R IN 50 R/W R IN R IN 51 CE V DD (+5V) 52 L IN 1 CE 2 R/W L IN L IN 5 A10 3 BUSY L IN L IN 6 OE 4 INT L OUT L IN 7 A0 - TOP VIEW - 46 OE A1 L IN 8 A2 L IN

CY7C1461V25

Abstract: CY7C1463V25 CY7C1465V25
Contextual Info: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M x 36/2M × 18/512K × 72 common I/O

CY7C132

Abstract: CY7C136 CY7C146
Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports

Contextual Info: CY7C1460AV33 CY7C1462AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■

CY7C136-55NI

Abstract: cy7c136 CY7C132 CY7C142 CY7C146 CY7C146-15NC CY7C136-25JXC CY7C136-55NC
Contextual Info: CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells that enable simultaneous reads of the same memory location ■ 2K x 8 organization ■ 0.65 micron CMOS for optimum speed and power

CY7C1464AV33-167BGI

Abstract: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 CY7C1462AV33-200AXC
Contextual Info: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states

CY7C1464AV33-167BGI

Abstract: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 cypress nobl 1-Mbit sram
Contextual Info: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states

CY7C1462AV25

Abstract: CY7C1460AV25 CY7C1464AV25
Contextual Info: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states

Z1213

Abstract: CY7C132 CY7C136 CY7C146 zl12
Contextual Info: bSE » CYPRESS SEMICONDUCTOR SSÖ'lbbE 0 0 0 ^ 7 4 7 ISb I CYP CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR 2K x 8 Dual-Port Static RAM output enable OE . BUSY flags are pro­ vided on each port. In addition, an interrupt Functional Description Features

Contextual Info: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states

Contextual Info: CY7C1460AV33 CY7C1462AV33 36-Mbit 1 M x 36/2 M × 18 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■

CY7C1460AV25

Abstract: CY7C1462AV25 CY7C1464AV25
Contextual Info: CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Pipelined SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

C-136B

Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS 2K x 8 Dual-Port Static RAM F ea tu res F u n ctio n al D escrip tio n • 0 .8 -m icro n C M O S for optim u m speed/ pow er • A u to m atic power-down • T T L com p atib le • C ap ab le o f w ith stan d in g g re a te r th an

30l3l

Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 CYPRESS SEMICONDUCTOR F eatures F unctional D escription • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation

CY7C1461AV33

Abstract: CY7C1463AV33 CY7C1465AV33
Contextual Info: CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 36-Mbit 1M x 36/2 M x 18/512K x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait

CY7C136-55NI

Abstract: CY7C146 idt7132 CY7C132 CY7C136 PC TO IDT7132 CY7C136-55NC
Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns

05353

Abstract: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33
Contextual Info: CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT ■ Supports 250 MHz Bus Operations with Zero Wait States

CY7C1461AV33

Abstract: CY7C1463AV33 CY7C1465AV33
Contextual Info: CY7C1461AV33 CY7C1463AV33, CY7C1465AV33 36-Mbit 1 M x 36/2 M × 18/512 K × 72 Flow-Through SRAM with NoBL Architecture 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

250ac to 30 v ac

Abstract: CY7C1462V25 CY7C1464V25 CY7C1460V25
Contextual Info: CY7C1460V25 CY7C1462V25 CY7C1464V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns

HA 13645

Contextual Info: fax id: 5201 CY7C132/CY7C136 CY7C142/CY7C146 2Kx8 Dual-Port Static RAM Featu res Functional Description • True Dual-Ported memory cells which allow sim ulta­ neous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power

C13220

Abstract: C1328 C1327 CY7C132 CY7C136 CY7C146 C1323 CY7C136-55NC
Contextual Info: CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 DualĆPort Static RAM output enable OE . BUSY flags are proĆ vided on each port. In addition, an interĆ rupt flag (INT) is provided on each port of the 52Ćpin LCC and PLCC versions. BUSY signals that the port is trying to access the