CY7C1350 Search Results
CY7C1350 Price and Stock
Cypress Semiconductor CY7C1350G-133AXINO WARRANTY |
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CY7C1350G-133AXI | 611 |
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CY7C1350G-133AXI | 1,210 | 1 |
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CY7C1350G-133AXI | 2,803 |
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Cypress Semiconductor CY7C1350G-133AXCNO WARRANTY |
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CY7C1350G-133AXC | 2,803 |
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CY7C1350G-133AXC | 6,107 |
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Rochester Electronics LLC CY7C1350B-133AIIC SRAM 4.5MBIT PAR 100TQFP |
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CY7C1350B-133AI | Bulk | 77 |
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FLIP ELECTRONICS CY7C1350G-200AXCNO WARRANTY |
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Rochester Electronics LLC CY7C1350G-200AXCZBT SRAM, 128KX36, 2.8NS PQFP100 |
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CY7C1350G-200AXC | Bulk | 53 |
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CY7C1350 Datasheets (81)
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ECAD Model |
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Description |
Curated |
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CY7C1350 |
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128Kx36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350 |
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NoBL, The ZBT-Compatible Family | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350-100AC |
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128K x 36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350-100AC |
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128Kx36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350-133AC |
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128K x 36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350-133AC |
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128Kx36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350-143AC |
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128K x 36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350-143AC |
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128Kx36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350-80AC |
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128K x 36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350-80AC |
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128Kx36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350B |
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128Kx36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350B-143AC |
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128Kx36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350B-150AC |
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128Kx36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350B-166AC |
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128Kx36 Pipelined SRAM with NoBL Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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CY7C1350F |
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4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350F-100AC |
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4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture | Original | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1350F-100AI |
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CY7C1350F-100BGC |
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CY7C1350F-100BGI |
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CY7C1350F-133AC |
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4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture | Original |
CY7C1350 Datasheets Context Search
Catalog Datasheet |
Type |
Document Tags |
PDF |
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CY7C1350
Abstract: IDT71V546 MCM63Z736
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Original |
CY7C1350 128Kx36 IDT71V546, MT55L128L36P MCM63Z736 143-MHz CY7C1350 IDT71V546 MCM63Z736 | |
CY7C1350Contextual Info: fax id: 1103 * g S S M ^ % rrv rt n n n CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture F e a tu re s F u n c t io n a l D e s c r ip t io n • Pin compatible and functionally e q u iv a le n ts ZBT™ devices IDT71V546, MT55L128L36P and MCM63Z736 |
OCR Scan |
CY7C1350 128Kx36 IDT71V546, MT55L128L36P MCM63Z736 CY7C1350 143-MHz | |
CY7C1350B-80AC
Abstract: CY7C1350B
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Original |
CY7C1350B 128Kx36 IDT71V546, MT55L128L36P, MCM63Z736 166-MHz 150-MHz 143-MHz 133-MHz CY7C1350B-80AC CY7C1350B | |
CY7C1350F
Abstract: CY7C1350F-250AC CY7C1350F-250AI CY7C1350F-250BGC
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1CY7C1350F CY7C1350F CY7C1350F CY7C1350F-250AC CY7C1350F-250AI CY7C1350F-250BGC | |
CY7C1350GContextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability |
Original |
CY7C1350G CY7C1350G A100RA | |
CY7C1350GContextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need |
Original |
CY7C1350G 250-MHz 100-pin 119-ball CY7C1350G | |
CY7C1350F
Abstract: CY7C1350F-250AC CY7C1350F-250AI CY7C1350F-250BGC
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Original |
1CY7C1350F CY7C1350F CY7C1350F CY7C1350F-250AC CY7C1350F-250AI CY7C1350F-250BGC | |
CY7C1350Contextual Info: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Supports 143-MHz bus operations with zero wait states—Data is transferred on every clock The CY7C1350 is a 3.3V 128K by 36 synchronous-pipelined |
Original |
CY7C1350 128Kx36 143-MHz CY7C1350 | |
CY7C1350
Abstract: IDT71V546 MCM63Z736
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Original |
CY7C1350 128Kx36 IDT71V546, MT55L128L36P MCM63Z736 143-MHz CY7C1350 IDT71V546 MCM63Z736 | |
Contextual Info: 350A CY7C1350A/GVT71128ZC36 128Kx36 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 143, 133 and 100 MHzInternally synchronized registered outputs eliminate the need to control OE |
Original |
CY7C1350A/GVT71128ZC36 128Kx36 CY7C1350A/GVT71128ZC36 | |
CY7C1350
Abstract: CY7C1351 CY7C1353
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Original |
CY7C1350 CY7C1351 CT7C1352 CY7C1353 CY7C1350/1351/1352/1353 CY7C1352-AC 30C/60 CY7C1350-AC CY7C1350 CY7C1351 CY7C1353 | |
CY7C1350GContextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need |
Original |
CY7C1350G 250-MHz 100-pin 119-ball CY7C1350G | |
CY7C1350B
Abstract: CY7C1329 CY7C1351B CY7C1352B CY7C1353B
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Original |
R52D-3 CY7C1350B CY7C1351B CY7C1352B CY7C1353B CY7C1329-AC 30C/60 CY7C1350B CY7C1329 CY7C1351B CY7C1352B CY7C1353B | |
Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need |
Original |
CY7C1350G 200-MHz 100-pin | |
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CY7C1350BContextual Info: CY7C1350B PRELIMINARY CY7C1350B 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736 • Supports 166-MHz bus operations with zero wait states |
Original |
1CY7C1350B CY7C1350B 128Kx36 IDT71V546, MT55L128L36P, MCM63Z736 166-MHz 150-MHz 143-MHz CY7C1350B | |
CY7C1350B
Abstract: 350B IDT71V546 MCM63Z736 DP330
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Original |
CY7C1350B 128Kx36 IDT71V546, MT55L128L36P, MCM63Z736 166-MHz 150-MHz 143-MHz 133-MHz CY7C1350B 350B IDT71V546 MCM63Z736 DP330 | |
CY7C1350GContextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability |
Original |
CY7C1350G CY7C1350G | |
Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need |
Original |
CY7C1350G CY7C1350G | |
CY7C1350FContextual Info: 350F PRELIMINARY CY7C1350F 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Fully registered inputs and outputs for pipelined |
Original |
CY7C1350F 128Kx36 250-MHz CY7C1350F | |
Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Functional Description Features • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need |
Original |
CY7C1350G 200-MHz 100-pin | |
CY7C1350GContextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability |
Original |
CY7C1350G CY7C1350G | |
Contextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability |
Original |
CY7C1350G 250-MHz 200-MHz 166-MHz 133-MHz A100RA | |
A8299Contextual Info: CY7C1350G 4-Mbit 128 K x 36 Pipelined SRAM with NoBL Architecture 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need |
Original |
CY7C1350G CY7C1350G A8299 | |
Contextual Info: CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability |
Original |
CY7C1350G 250-MHz 200-MHz 166-MHz 133-MHz 100-MHz 100-pin 119-ball |