CY7C330 Search Results

Contextual Info: CY7C330 C Y P R E S S •0 Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

Contextual Info: CY7C330: Saturday, January 4, 1992 Revision: October 19, 1995 CY7C330 Features D Twelve I/O macrocells each having: Ċ registered, threeĆstate I/O pins Ċ input register clock select multiĆ plexer D Ċ feed back multiplexer Ċ output enable OE multiplexer

Contextual Info: This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. For new designs, please refer to the CY7C33S. CY7C330 CMOS Programmable Synchronous State Machine CYPRESS SEMICONDUCTOR Features Three separate clocks— two inputs,

CY7C330

Contextual Info: fax id: 6019 1CY 7C33 0 CY7C330 CMOS Programmable Synchronous State Machine • 66-MHz operation — 3-ns input set-up and 12-ns clock to output Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — 15-ns input register clock to state register clock

CY7C330-50TMB

Abstract: CY7C330 7C330
Contextual Info: CY7C330 '# C Y P R E S S Features • TVelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

cy7c330

Contextual Info: CY7C330 CYPRESS SEMICONDUCTOR CMOS Programmable Synchronous State Machine Features • 256 product terms— 32 per pair of macro cells, variable distribution 12 I /O macro cells each having: — registered, three-state I /O pins — input register clock select

Contextual Info: CY7C330 / CYPRESS Features • TVvelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi* plexer — feed back multiplexer — output enable OE multiplexer • AH twelve macrocell state registers can be hidden

Contextual Info: CY7C330 '# C Y P R E S S CMOS Programmable Synchronous State Machine Three separate clocks— two inputs, one output Common pin 14-co n tro lled or product term —controlled output en­ able for each I/O pin 256 product terms—32 per pair of macrocells, variable distribution

Contextual Info: CY7C330 CYPRESS SEMICONDUCTOR CMOS Programmable Synchronous State Machine Features • 12 I / O m acro cells each having: — registered, three-state I /O pins — input register clock select m ultiplexer — feed back m ultiplexer — output enable O E

7C330

Abstract: lestat
Contextual Info: acI2£ S ’ is T& CY7C330 O Y P P R '- y s — •— - SEMICONDUCTOR Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer

Contextual Info: CY7C330 > CYPRESS CMOS Programmable Synchronous State Machine • 28-pin, 300-mil DIP, LCC Three separate clocks— two inputs, one output Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select m ulti­

L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

Contextual Info: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin

Contextual Info: fax id: 6018 CY7C335 Universal Synchronous EPLD — 2-ns input set-up and 9-n s o u tp u t re g is te r clo c k to o u tp u t Featu res • 1 0 0-M H z o u tp u t registered o peration — 10-ns inp u t re g is te r clo ck to sta te re g is te r clo ck • Tw elve I/O m acrocells, each having:

TCO - 909 F 10 MHz

Abstract: TCO - 909 C335 CY7C335 TCO - 909 F C335A
Contextual Info: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

C3357

Abstract: c3358 CERAMIC LEADLESS CHIP CARRIER diode c335 c3356 c3355 C335 CY7C335-66PC CY7C335 C3354
Contextual Info: fax id: 6018 1CY 7C33 5 CY7C335 Universal Synchronous EPLD Features — 2-ns input set-up and 9-ns output register clock to output • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — 10-ns input register clock to state register clock

TCO - 909 F 10 MHz

Abstract: TCO - 909 F CERAMIC LEADLESS CHIP CARRIER C335 CY7C335
Contextual Info: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

CY62256LL-PC

Abstract: VIC068A-GC VIC64-NC VIC64-UMB PALCE22V10-JI PALC16L8Q PLD VME A113 CY7B923 JESD22-A113
Contextual Info: Cypress Semiconductor Product Reliability 1997 Published June, 1997 CYPRESS SEMICONDUCTOR PRODUCT RELIABILITY TABLE OF CONTENTS 1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM. 1 2.0 ELECTRICAL AVERAGE OUTGOING QUALITY. 2

C3317

Abstract: L1190 CY7331
Contextual Info: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all

Contextual Info: CY7C332 CYPRESS Features • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product term s (PTs) per output — Product term (PT) output polarity

Contextual Info: CY7C331 CYPRESS — . = SEMICONDUCTOR Asynchronous Registered EPLD T\velve I/O macrocells each having: — One state flip-flop with an XOR sura-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set,

Contextual Info: _ CY7C335 Universal Synchronous EPLD SEMICONDUCTOR Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer

Contextual Info: Introduction to Cypress PLDs r ^ y p p p c c SEMICONDUCTOR Cypress PLD Family Features T h e P L D fam ily im p le m e n ts th e fam iliar “ su m o f p ro d u c ts ” logic b y using a p ro g ra m m a b le A N D a rra y w h o se o u tp u t te rm s feed a

Contextual Info: fax id: 6019 CMOS Programmable Synchronous State Machine Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — Input register clock select multiplexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers can be hidden