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L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

Contextual Info: CY7C330 C Y P R E S S •0 Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

Contextual Info: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin

transistor c331

Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
Contextual Info: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the

C3317

Abstract: L1190 CY7331
Contextual Info: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all

Contextual Info: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Generic architecture to replace stan­ dard logic functions including: 20L10, 20L8,20R8,20R6,20R4,12L10,14L8, 16L6,18L4,20L2, and 20V8 Eight product term s and one OE product term per output

Contextual Info: CY7C335 / CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect m ultiplexer — Feed back multiplexer — Output enable OE multiplexer

20G10B-20

Abstract: 12L10 16L6 18L4 20L10 20L8
Contextual Info: r PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpn = 15 ns, tc o = ID us, tg = 12 ns — Military: tPD = 20 ns, tc o = 15 ns, ts — 15 ns • Low power — Ice max.: 70 mA, commercial — Ic e max.: 100 mA, military • Commercial and m ilitary tem perature

aj4 diode

Abstract: CY7C277 658f 7C277
Contextual Info: CYPRESS 4bE SEMICONDUCTOR J /s S - I SSfl'lbbS GG0bôb3 fl B C Y P D CY7C277 CY7C279 CYPRESS SEMICONDUCTOR Reprogrammable 32K x 8 Registered PROM Programmable address latch enable input Programmable synchronous or asynchronous output enable 7C277 On-chip edge-triggered output

transistor c331

Abstract: c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet
Contextual Info: fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable

2SUR

Abstract: CY7C331 L1190 C3317
Contextual Info: CY7C331 ¿F C Y P R E S S Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set, reset, and clock inpnts on all

Contextual Info: CY7C277 CY7C279 CYPRESS SEMICONDUCTOR Features Reprogrammable 32K x 8 Registered PROM Programmable address latch enable input Programmable synchronous or asynchronous output enable 7C277 On-chip edge-triggered output registers (7C277) Optional registered/latched address

Contextual Info: s rs y CYPRESS SEMICONDUCTOR Features • TWelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

imax6

Contextual Info: P / CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macroceils, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — O utput enable OE multiplexer

Contextual Info: CY7C277 CYPRESS SEMICONDUCTOR Reprogrammable 32K x 8 Registered PROM • Programmable address latch enable input • Programmable synchronous or asynchronous output enable • On-chip edge-triggered output registers • EPROM technology, 100% programmable

c331 equivalent

Abstract: C3317 c331-12 c3311 192x pin diagram c331
Contextual Info: CY7C331 Asynchronous Registered EPLD • Low power — 90 mA typical ICC quiescent Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the I/O

PALC22V10

Abstract: 22V10-35 PALC22V10-25dmb PALC22V10-40DMB PALC22V10L35PC PALC22V10 20HC PALC22V10L-25JC PALC22V10-35PC
Contextual Info: PALC22V10 CYPRESS SEMICONDUCTOR • Up to 22 input terms and 10 outputs • High reliability — Proven EPROM technology — 100% programming and functional testing Features • Advanced second-generation PAL architecture • Low power — 55 mA max. “IT

7C332

Contextual Info: CY7C335 Universal Synchronous EPLD V CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer