DM74LS27 Search Results

LS279

Abstract: 54LS279 54LS279DMQB 54LS279FMQB 54LS279LMQB DM54LS279 DM54LS279J DM74LS279 DM74LS279M DM74LS279N
Contextual Info: 54LS279 DM54LS279 DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent SetReset Latches with active low inputs Two of the four latches have an additonal S input ANDed with the primary S input A low on any S input while the R input is high will be

Contextual Info: S E M IC O N D U C T O R tm DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a com m on C lock and an asynchronous active LOW M aster Reset. This device is supplied in a 20-pin

Contextual Info: S E M IC O N D U C T O R tm DM74LS27 Triple 3-Input NOR Gates General Description This device contains three independent gates each of which perform s the logic NOR function. Connection Diagram Dual-ln-Line Package Vcc Cl 114 Y1 13 C3 63 11 12 A3 1D L rk 8

74LS279N

Abstract: 54LS279W of 74ls279
Contextual Info: S E M IC O N D U C T O R tm DM74LS279 Quad S -R Latches and S inputs from lo w to high will cause the Q output to be in­ determ inate. Both inputs are voltage level triggered and are not affected by transition tim e o f th e input data. General Description

DM74LS27

Abstract: DM54LS27E DM54LS27J DM54LS27W DM74LS27M DM74LS27N E20A J14A M14A
Contextual Info: DM74LS27 Triple 3-Input NOR Gates General Description This device contains three independent gates each of which performs the logic NOR function. Connection Diagram Dual-In-Line Package DS006359-1 Order Number DM54LS27J, DM54LS27W, DM54LS27E, DM74LS27M or DM74LS27N

Contextual Info: 54LS279,DM54LS279,DM74LS279 54LS279 DM54LS279 DM54LS279 Quad S-R Latches Literature Number: SNOS299A 54LS279 DM54LS279 DM74LS279 Quad S-R Latches General Description to be indeterminate Both inputs are voltage level triggered and are not affected by transition time of the input data

LS279

Abstract: IC DM74LS279N
Contextual Info: LS279 National JümSemiconductor 54LS279/DM54LS279/DM74LS279 Quad S-R Latches General Description to be indeterminate. Both inputs are voltage level triggered and are not affected by transition time of the input data. The ’LS279 consists of four individual and independent SetReset Latches with active low inputs. Two of the four latch­

54LS27

Abstract: 54LS27DMQB 54LS27FMQB 54LS27LMQB DM54LS27J DM54LS27W DM74LS27M DM74LS27N E20A
Contextual Info: LS27 £ 2 National Semiconductor 54LS27/DM54LS27/DM74LS27 Triple 3-Input NOR Gates General Description Features This device contains three independent gates each of which performs the logic NOR function. • Alternate Military/Aerospace device 54LS27 is avail­

74LS27

Abstract: DM74LS27 DM74LS27M DM74LS27N M14A MS-001 N14A
Contextual Info: Revised March 2000 DM74LS27 Triple 3-Input NOR Gate General Description This device contains three independent gates each of which performs the logic NOR function. Ordering Code: Order Number Package Number Package Description DM74LS27M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150 Narrow

Contextual Info: S E M IC O N D U C T O R tm DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register, consisting o f eight D -type flip-flops with a com m on C lock and an asynchronous active LOW M aster Reset. This device is supplied in a 20-pin

ls273

Abstract: 54LS273F
Contextual Info: LS273 a National Semiconductor 54LS273/DM74LS273 8-Bit Register with Clear General Description Features The 'LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20pin package featuring 0.3 inch row spacing.

Contextual Info: DM54LS273,DM74LS273 DM54LS273 DM74LS273 8-Bit Register with Clear Literature Number: SNOS298A DM54LS273 DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register consisting of eight D-type flip-flops with a common Clock and an asynchronous

Contextual Info: DM54LS273 DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset This device is supplied in a 20pin package featuring 0 3 inch row spacing

LS273

Abstract: DM54LS273 DM54LS273E DM54LS273J DM54LS273W DM74LS273 DM74LS273M DM74LS273N E20A J20A
Contextual Info: DM54LS273 DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset This device is supplied in a 20pin package featuring 0 3 inch row spacing

DM54LS27

Abstract: DM54LS27E DM54LS27J DM54LS27W DM74LS27 DM74LS27M DM74LS27N E20A J14A M14A
Contextual Info: DM54LS27 DM74LS27 Triple 3-Input NOR Gates General Description This device contains three independent gates each of which performs the logic NOR function Connection Diagram Dual-In-Line Package TL F 6359 – 1 Order Number DM54LS27J DM54LS27W DM54LS27E DM74LS27M or DM74LS27N

Contextual Info: May 1992 DM54LS27/DM74LS27 Triple 3-Input NOR Gates General Description This device contains three independent gates each of which performs the logic NOR function. Connection Diagram Dual-In-Line Package Vcc C1 Y1 C3 B3 A3 Y3 TL/F/6359-1 Order Number DM54LS27J, DM54LS27W,

54LS279DMQB

Abstract: 54LS279FMQB 54LS279LMQB DM54LS279J DM74LS279M DM74LS279N E20A J16A LS279
Contextual Info: & 54LS279/DM54LS279/DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent SetReset Latches with active low inputs. Two of the four latch­ es have an additonal S input ANDed with the primary S input. A low on any S input while the R input is high will be

BS011

Contextual Info: DM54LS273/DM74LS273 8-Bit Register with Clear National Semiconductor DM54LS273/DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a common Clock and an asynchronous

ls273

Abstract: 54LS273F
Contextual Info: LS273 NATIONAL SEMICOND -CLOGIO 31E D L.SD1125 D 0 7 G G 3 4 National Semiconductor T-H é>-& ï- 0 5 54LS273/DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register, consisting of eight D-type tiip-flops with a common Clock and an asynchronous

DM74LS27N

Contextual Info: May 1992 Semiconductor DM54LS27/DM74LS27 Triple 3-Input NOR Gates General Description This device contains three independent gates each of which performs the logic NOR function. Connection Diagram Dual-ln-Line Package T L /F /6 3 5 9 -1 Order Number DM54LS27J, DM54LS27W,

DM74LS273

Abstract: ls273 DM74LS273N E20A J20A DM54LS273E DM54LS273J DM54LS273W DM74LS273M
Contextual Info: DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch row spacing.

Contextual Info: DM54LS273 DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset This device is supplied in a 20pin package featuring 0 3 inch row spacing

DM54LS27E

Abstract: DM54LS27J DM54LS27W DM74LS27M DM74LS27N E20A J14A M14A N14A
Contextual Info: /* ! National . M ay 1992 Semiconductor DM54LS27/DM74LS27 Triple 3-Input NOR Gates General Description This device contains three independent gates each of w hich perform s th e logic NOR function. Connection Diagram Dual-In-Line Package Vcc C1 114 Y1 13 C3

54LS279

Abstract: 54LS279DMQB 54LS279FMQB 54LS279LMQB DM54LS279J DM74LS279 DM74LS279M DM74LS279N E20A J16A
Contextual Info: S E M IC O N D U C T O R tm DM74LS279 Quad H -R Latches General Description and S inputs from low to high will cause the Q output to be in­ determ inate. Both inputs are voltage level triggered and are not affected by transition tim e o f th e input data.