DS313 Search Results

XCF00S

Abstract: spartan 3a FGG900 DS099 XCN07010
Contextual Info: ds313.fm Page 1 Friday, April 18, 2008 10:26 AM Spartan-3L Low Power FPGA Family R DS313 v1.2 April 18, 2008 Product Specification This product is undergoing discontinuance. Please refer to XCN07010, Product Discontinuation Notice, for more information on last-time purchases and replacement products.

hdlc

Abstract: 070C 071C DS3134
Contextual Info: Application Note 364 DS3134 Step By Step Configuration-Bridge Mode www.dalsemi.com Overview This application note describes an example of how to configure a single T1 port on the DS3134 operating in Bridge Mode. Additionally, this example describes how to construct, send, receive, and check a packet

SPARTAN-3

Abstract: DS099 XCF00S FGG900
Contextual Info: ds313.fm Page 1 Thursday, September 15, 2005 11:39 AM Spartan-3L Low Power FPGA Family R DS313 v1.1 September 15, 2005 Preliminary Product Specification Introduction Spartan -3L Field-Programmable Gate Arrays (FPGAs) consume less static current than corresponding members

TP31C

Abstract: r02f Boss NS-2 PAB1 td33 LDO DS3131 DS3134 LA10 LA12 TD39
Contextual Info: DALLAS SEM ICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999

D3702

Abstract: SP1404 SP1404BW GEC Plessey Semiconductors
Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS SP1404BW, D3702 ADVANCE INFORMATION DS3139-2.0 SP1404BW HIGH VOLTAGE INTERFACE CIRCUIT The SP1404 is a bipolar integrated circuit comprising five individual digital current amplifier circuits. Each circuit accepts

D3702

Abstract: SP1404 SP1404BW
Contextual Info: SP1404BW, D3702 ADVANCE INFORMATION DS3139-2.0 SP1404BW HIGH VOLTAGE INTERFACE CIRCUIT The SP1404 is a bipolar integrated circuit comprising five individual digital current amplifier circuits. Each circuit accepts a logic input from TTL, CMOS or a similar source and drives a

ISO3309 hdlc

Abstract: MV6001
Contextual Info: MV6001 ADVANCE INFORMATION DS3138-2.1 MV6001 HDLC/DMA CONTROLLER The MV6001 is a combined HDLC transceiver and DMA controller capable of providing serial communications at rates up to 128K bits/second, and handling direct memory access clock rates up to 8MHz.

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS SP1404BW, D3702 ADVANCE INFORMATION DS3139-2.0 SP1404BW HIGH VOLTAGE INTERFACE CIRCUIT The SP1404 is a bipolar integrated circuit comprising five individual digital current amplifier circuits. Each circuit accepts

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS MV3506/7/8 ADVANCE INFORMATION DS3133-2.1 MV3506 MV3507 MV3508 A-LAW FILTER/CODEC µ-LAW FILTER/CODEC A-LAW FILTER/CODEC WITH OPTIONAL SQUELCH These devices are silicon gate CMOS Companding

LA0-RD37

Contextual Info: PRELIMINARY DS3131 BoSS Bit SynchronouS HDLC Controller www.maxim-ic.com FEATURES § § § § § § 40 timing independent bit synchronous ports 40Rx and 40Tx coupled with 40 independent Bidirectional HDLC channels Each port can operate up to 52 Mbps 132Mbps full-duplex throughput

hdlc

Abstract: 071C DS3134 070C
Contextual Info: Application Note 363 DS3134 Step By Step Configuration-Configuration Mode www.dalsemi.com Overview This application note describes an example of how to configure a single T1 port on the DS3134 operating in configuration mode. Additionally, this example describes how to construct, send, receive, and check a

Contextual Info: DALLAS SEM ICONDUCTOR DS3131 Preliminary Data Sheet V1 August 6, 1998 DALLAS SEMICONDUCTOR DS3131 BOSS Bit and Octet Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Options for Local Bus Access & an Octet Synchronous Port Preliminary Data Sheet

HDLC 3309 1993

Abstract: DS3134 RS15 TD15 TS15 33091
Contextual Info: PRELIMINARY DS3134 Chateau – Channelized T1 And E1 And HDLC Controller www.dalsemi.com FEATURES • • • • • • • • • • 256 Channel HDLC Controller that Supports up to 64 T1 or E1 Lines or Two T3 Lines 256 Independent bi-directional HDLC

ZNPCM2

Abstract: GEC plessey 18 pin 12 channel ir decoder ic plessey application note an 112
Contextual Info: GEC PLESSEY I s e m i c o n d u c t o r s ] DS3135-1.0 ZNPCM1 SINGLE CHANNEL CODEC FEATURES • Converts a Delta-Sigma Modulated Digital Pulse Stream into Compressed 'A'-Law PCM and

PSA B20 0110

Abstract: pabi DS3134 LA10 LA12 LA15
Contextual Info: DALLAS SEM ICONDUCTOR DS3134 Preliminary Data Sheet V4 November 18, 1998 DALLAS SEMICONDUCTOR DS3134 CHATEAU CHAnnelized T1 and E1 And Universal HDLC CONTROLLER 256 Channel HDLC Controller that Supports up to 64 T1 or E1 Lines or Two T3 Lines Preliminary Data Sheet

DS099-2

Abstract: DS099 XCF00S FGG320
Contextual Info: ds313.fm Page 1 Wednesday, November 3, 2004 5:48 PM Spartan-3L Low Power FPGA Family R DS313 v1.0 November 3, 2004 Introduction • Spartan -3L Field-Programmable Gate Arrays (FPGAs) consume less static current than corresponding members of the standard Spartan-3 family. Spartan-3L devices provide the identical function, features, timing, and pinout of the

TH21C

Abstract: TP31C hdlc 11-B DS3131 TD39
Contextual Info: DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous BoSS HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for

DS3133-2

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS MV3506/7/8 ADVANCE INFORMATION DS3133-2.1 MV3506 MV3507 MV3508 A-LAW FILTER/CODEC µ-LAW FILTER/CODEC A-LAW FILTER/CODEC WITH OPTIONAL SQUELCH These devices are silicon gate CMOS Companding

Contextual Info: THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS MV6001 ADVANCE INFORMATION DS3138-2.1 MV6001 HDLC/DMA CONTROLLER The MV6001 is a combined HDLC transceiver and DMA controller capable of providing serial communications at rates

ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME

Abstract: Channels64 ROUND ROBIN ARBITRATION AND FIXED PRIORITY hdlc DS31256 DS3131 DS3134
Contextual Info: Application Note 2351 DS31256 and DS3134 HDLC Controller Comparisons www.maxim-ic.com INTRODUCTION This application note compares the differences between the DS3134 CHATEAU and the DS31256 Envoy HDLC controllers. The most important difference is that all known DS3134 errata have been fixed in DS31256, and the

Contextual Info: DALLAS SEMICONDUCTOR DS3134 Preliminary Data Sheet V5 September 1, 1999 DALLAS SEMICONDUCTOR DS3134 CHATEAU CHAnnelized T1 and E1 And Universal HDLC CONTROLLER 256 Channel HDLC Controller that Supports up to 56 T1 or E1 Lines or Two T3 Lines Preliminary Data Sheet

Contextual Info: DALLAS SEMICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999

TP31C

Abstract: DS3131 DS3134 LA10 LA12 TD39 811B
Contextual Info: DALLAS SEMICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit SynchronouS HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999

0X008H

Contextual Info: PRELIMINARY DS3134 Chateau – Channelized T1 And E1 And HDLC Controller www.dalsemi.com FEATURES • • • • • • • • • • 256 Channel HDLC Controller that Supports up to 64 T1 or E1 Lines or Two T3 Lines 256 Independent bi-directional HDLC