SSTL18 Search Results

Contextual Info: TPS51116 www.ti.com SLUS609C – MAY 2004 – REVISED APRIL 2005 COMPLETE DDR AND DDR2 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE FEATURES • • DESCRIPTION Synchronous Buck Controller VDDQ – Wide-Input Voltage Range: 3.0-V to 28-V

Contextual Info: Preliminary Datasheet 1.5A DDR TERMINATION REGULATOR AP2301 General Description Features The AP2301 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM. The regulator can sink or source up to 1.5A current continuously, offers enough

ep4cgx30f484

Abstract: EP4CE115 CYIV-5V1-1 EP4CGX EP4CE55 EP4CE15 sigma delta lcd screen lvds 40 pin diagram ep4ce22 ep4ce40
Contextual Info: Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.5 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

lpddr3

Abstract: lpddr3 controller LPDDR3 layout TPS59116 str 5 q 0765 POWER SUPPLY CIRCUIT IRF7821 IRF7832 SSTL-18 DDR3 layout TI
Contextual Info: TI Information — Selective Disclosure TPS59116 www.ti.com SLUSA57 – NOVEMBER 2010 Complete DDR, DDR2 and DDR3 Memory Power Solution Synchronous Buck Controller, 3-A LDO, Buffered Reference for Embedded Computing Systems Check for Samples: TPS59116 FEATURES

DDR2-667

Abstract: PC2-5300 SSTL-18
Contextual Info: NT256T64UH4A1FY 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 32Mx16 DDR2 SDRAM Features • JEDEC Standard 240-pin Dual In-Line Memory Module • 32Mx64 DDR2 Unbuffered DIMM based on 32Mx16 DDR2 SDRAM • Performance:

NT512T64U88A0BY-37B

Abstract: NT512T64U88A0BY-5A NT1GT64U8HA0BY-37B NT512T64U88A0F PC2-3200 SSTL-18 4E543147543634553848413042592D35412020 NT512T64U88A
Contextual Info: NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY Green NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 64Mx8 DDR2 SDRAM Features • JEDEC Standard 240-pin Dual In-Line Memory Module

NT5TU128M8DE

Abstract: NT5TU64M16DG nt5tu64m16dg-Bd NT5TU128M8DE-BD NT5TU256M4DE nt5tu64m NT5TU64M16 NT5TU64M16DG-3C NT5TU64M16DG-3CI NT5TU64M16DG-BE
Contextual Info: NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG NT5TB256M4DE / NT5TB128M8DE / NT5TB64M16DG 1Gb DDR2 SDRAM Feature CAS Latency Frequency -37B/-37BI -3C/-3CI -AD/-ADI -AC/-ACI/-ACL -BE -BD DDR2-533 DDR2-667 DDR2-800 DDR2-800 DDR2-1066 DDR2-1066 4-4-4 5-5-5 6-6-6

nt5tu128m8de-ac

Abstract: NT5TU64M16DG-AD NT5TU128M8DE-AD NT5TU256M4DE NT5TU128M8DE NT5TU64M16DG NT5TU64M16DG-3C Nanya NT5TU64M16DG
Contextual Info: NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG 1Gb DDR2 SDRAM Preliminary Edition Features CAS Latency and Frequency Speed Sorts -37B DDR2 -533 -3C DDR2 -667 -AD DDR2 -800 -AC DDR2 -800 Units Bin CL-tRCD-TRP 4-4-4 5-5-5 6-6-6 5-5-5 tck max. Clock Frequency 266

NT5TU32M16AG-37B

Abstract: NT5TU128M4AE nt5tu64m8 nt5tu64m NT5TU32M16 NT5T nt5tu32m16ag nt5tu64m8af
Contextual Info: NT5TU128M4AB/NT5TU128M4AE Green NT5TU64M8AF/NT5TU64M8AB/NT5TU64M8AE(Green) ) 512Mb DDR2 SDRAM Features • Write Latency = Read Latency -1 CAS Latency and Frequency • Programmable Burst Length: 4 and 8

NT1GT64U8HA0BN

Abstract: NT1GT64U8HA0BN-3C DDR2-400 DDR2-533 DDR2-667 PC2-3200 PC2-5300 SSTL-18 NT1GT64U8HA0BN-37B
Contextual Info: NT1GT64U8HA0BN Green 1GB : 128M x 64 PC2-3200 / PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM 200 pin Unbuffered DDR2 SO-DIMM Based on 64Mx8 DDR2 SDRAM Features • 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) • 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx8 DDR2

NT5TU32M16CG-BD

Abstract: NT5TU32M16CG-be NT5TU64M8CE
Contextual Info: NT5TU128M4CE / NT5TU64M8CE /NT5TU32M16CG 512Mb DDR2 SDRAM C-Die Features • 1.8V ± 0.1V Power Supply Voltage • Data-Strobes: Bidirectional, Differential • Programmable CAS Latency: 3,4,5,6 and 7 • 4 internal memory banks • Programmable Additive Latency: 0, 1, 2, 3, and 4

XC3S700A

Abstract: xc3s200aft256 XC3S400AFT256 XC3S50A L01P L02P FG320 UG331 L05P xc3s400a ftg256
Contextual Info: Spartan-3A FPGA Family: Data Sheet R DS529 July 10, 2007 Product Specification Module 1: Introduction and Ordering Information - DS529-1 v1.4.1 July 10, 2007 • • • • • • • Introduction Features Architectural and Configuration Overview General I/O Capabilities

K4T51043QB-GCCC

Abstract: K4T51043QB-GCE6 K4T51043QB-GLE6
Contextual Info: Preliminary DDR2 SDRAM 512Mb B-die DDR2 SDRAM 512Mb B-die DDR2 SDRAM Specification Version 0.91 September 2003 Rev. 0.91 Sep. 2003 Page 1 of 38 Preliminary DDR2 SDRAM 512Mb B-die DDR2 SDRAM Contents 1. Key Feature 2. Package Pinout/Mechnical Dimension & Addressing

7F7F7F0B00000000

Abstract: PC2-5300 PC2-6400 NT512T64UH8B0FN NT1GT64U8HB0BN-3C 32MX16
Contextual Info: NT256T64UH4B0FN / NT512T64UH8B0FN NT1GT64U8HB0BN 256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64 PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM 200 pin Unbuffered DDR2 SO-DIMM Based on DDR2-533/667/800 32Mx16/64Mx8 SDRAM B-Die Features • Performance:

Contextual Info: TPS51116 www.ti.com SLUS609A – MAY 2004 – REVISED JUNE 2004 COMPLETE DDR AND DDR2 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE FEATURES • • DESCRIPTION Synchronous Buck Controller VDDQ – Wide-Input Voltage Range: 3.0-V to 28-V

7813 Texas Instruments Transistor

Abstract: TMS320C6000 TMS320C6474 C6000 C6474 C64X DDR2-667 SPRS552H BR17
Contextual Info: TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com TMS320C6474 Multicore Digital Signal Processor 1 Features 12 • Key Features – High-Performance Multicore DSP C6474 – Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns

OC48

Abstract: SSTL-15 SSTL-18
Contextual Info: Arria II Device Handbook Volume 3: Device Datasheet and Addendum Arria II Device Handbook Volume 3: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V3-4.0 Document last updated for Altera Complete Design Suite version:

Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications

transistor d880

Abstract: BR17
Contextual Info: TMS320C6474 www.ti.com SPRS552E – OCTOBER 2008 – REVISED APRIL 2010 TMS320C6474 Multicore Digital Signal Processor 1 Features 12 • Key Features – High-Performance Multicore DSP C6474 – Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns

XC3S700A-FG484

Abstract: XC3S700AFG484 MT47H32M16BN-3 MT47H32M16 LCD with picoblaze MT47H32M16BN MT47H32M16XX-5E T-2420 T2420 Thermonics T 2420
Contextual Info: Application Note: Spartan-3A FPGA Family Implementing DDR2-400 Memory Interfaces in Spartan-3A FPGAs R Author: Eric Crabill XAPP458 v1.0.1 July 9, 2009 Summary High-performance consumer products and their requirement for low-cost, high-bandwidth memory create demand for high-performance DDR2 memory interfaces. Xilinx offers a

Contextual Info: Artix-7 FPGAs Data Sheet: DC and Switching Characteristics DS181 v1.6 April 17, 2013 Product Specification Introduction Artix -7 FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance. The -2L devices can operate at either of two VCCINT voltages, 0.9V

Contextual Info: Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 v1.18 November 26, 2013 Product Specification Introduction Virtex -7 T and XT FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance.

Contextual Info: Cyclone V Device Datasheet February 2014 CV-51002-3.8 CV-51002-3.8 Datasheet This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Cyclone V devices. Cyclone V devices are offered in commercial and industrial grades. Commercial

TLC nand

Abstract: jz4760 ingenic D16-DDR tlc nand flash 1080P CCIR656 IEEE745 mobile color LCD DISPLAY PINOUT nand flash tlc
Contextual Info: JZ4760 Mobile Application Processor Data Sheet Release Date: Jan. 05, 2011 JZ4760 Mobile Application Processor Data Sheet Copyright 2005-2010 Ingenic Semiconductor Co. Ltd. All rights reserved. Disclaimer This documentation is provided for use with Ingenic products. No license to Ingenic property rights is