M48Z12 Search Results

DS1220

Abstract: M48Z02 M48Z12 24-Pin Plastic DIP
Contextual Info: M48Z02 M48Z12 5 V, 16 Kbit 2 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM and powerfail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection

M40Z300

Abstract: M48Z128 M48Z128V M48Z128Y SOH28
Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES

Contextual Info: /T T SGS-THOMSON M48Z02 A 7 # . [M»[g[LI gmMD(gS_ M48Z12 16Kb (2K x 8 ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ UNLIMITED WRITE CYCLES ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ AUTOMATIC POWER-FAIL CHIP DESELECT and

M48Z129V

Abstract: M48Z129Y
Contextual Info: M48Z129Y M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE

M48Z129V

Abstract: M48Z129Y
Contextual Info: M48Z129Y M48Z129V 5.0 V or 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of

PCDIP24

Abstract: M48Z02 Zeropower DS1220 M48Z02 M48Z12
Contextual Info: M48Z02 M48Z12 16Kb 2K x 8 ZEROPOWER SRAM DATA BRIEFING INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES

ram module 94v-0

Abstract: 94V-0* RAM E89556
Contextual Info: File E89556 Vol. 1 Sec. 2 Page 1 and Report Issued: 10-07-92 DESCRIPTION PRODUCT COVERED: * Component - Lithium Battery Powered Integrated Circuits with Lithium battery, Models M48Z34W, M48Z128W, M48Z129W, M48T128W, M48T129W, M48T512W, M48T513W, M48Z512AW, M48Z30W, M48T248W, M48T251W and M48Z2M1W, where

M48Z128

Abstract: M48Z128Y
Contextual Info: M48Z128 M48Z128Y CMOS 128K x 8 ZEROPOWER SRAM INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 128K x 8 SRAMs

Contextual Info: F Z J ^ 7 i SGS-THOMSON M48Z128 K» ô [iL[imMO(êS_ M48Z128Y 1 Mb (128K x 8) ZEROPOWER SRAM • INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS of DATA RETENTION in the

48z02

Abstract: MK48Z02-12
Contextual Info: SGS-THOMSON * 7 / . HD S@ilLI©TO ia gi M48Z02 M48Z12 r= 7 CMOS 2K x 8 ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ UNLIMITED WRiTE CYCLES ■ READ CYCLE TIME EQUALS WRiTE CYCLE TIME ■ AUTOMATIC POWER-FAL CHIP DESELECTand

AN1012

Abstract: DS1220 M48Z02 M48Z12
Contextual Info: M48Z02 M48Z12 5 V, 16 Kbit 2 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM and powerfail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection

D 4242

Contextual Info: M48Z129Y M48Z129V 1 Mbit 128Kb x8 ZEROPOWER SRAM PRELIMINARY DATA INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER MICROPROCESSOR POWER-ON RESET

Contextual Info: M48Z128 M48Z128Y ¿= 7 S G S -T H O M S O N ^ 7 # M IE m [i(g]rO M O (§S 1Mb (128K x 8 ZEROPOWER SRAM « INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY • CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS of DATA RETENTION in the

D 4242

Abstract: PMDIP32 M48Z129V M48Z129Y
Contextual Info: M48Z129Y M48Z129V 1Mb 128K x 8 ZEROPOWER SRAM PRELIMINARY DATA INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER MICROPROCESSOR POWER-ON RESET

Contextual Info: M48Z02 M48Z12 5 V, 16 Kbit 2 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM and powerfail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection

PMDIP32

Contextual Info: M48Z128 M48Z128Y CMOS 128K x 8 ZEROPOWER SRAM DATA BRIEFING INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER PIN and FUNCTION COMPATIBLE with

Contextual Info: 5 ï. S G S -1H 0M S 0N ILIMMûiêS M48Z129Y M48Z129V 1Mb 128K x 8 ZEROPOWER SRAM PRELIMINARY DATA • INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS of DATA RETENTION in the

sram 2k x 8

Contextual Info: M48Z02 M48Z12 CMOS 2K x 8 ZEROPOWER SRAM DATA BRIEFING INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECTand WRITE PROTECTION CHOICE of TWO WRITE PROTECT

AN1012

Abstract: M48Z129V M48Z129Y
Contextual Info: M48Z129Y M48Z129V 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION ■ MICROPROCESSOR POWER-ON RESET (RESET VALID EVEN DURING BATTERY

Contextual Info: M48Z129Y M48Z129V SGS-THOMSON ra [iôm[iOT s Ki(gs 1Mb (128K x 8) ZEROPOWER SRAM PRELIMINARY DATA INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER

M48Z128

Abstract: M48Z128Y SOH28 TSOP32
Contextual Info: M48Z128 M48Z128Y 1 Mbit 128Kb x8 ZEROPOWER SRAM • INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS of DATA RETENTION in the ABSENCE of POWER ■ AUTOMATIC POWER-FAIL CHIP DESELECT

Contextual Info: M48Z129V 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of

Contextual Info: M48Z128 M48Z128Y / S T SGS-THOMSON ^ 7# MO K&I(iM®KflD^ CMOS 128K x 8 ZEROPOWER SRAM PRELIMINARY DATA • INTEGRATED LOW POWER SRAM, POWERFAIL CONTROL CIRCUIT AND BATTERY ■ CONVENTIONAL SRAM OPERATION; UN­ LIMITED WRITE CYCLES ■ 10 YEAR MINIMUM DATA RETENTION IN THE

Contextual Info: / ^ T SGS-THOM SON ^ 7 #» MWilLIIgiiìMDgS M48Z129Y M48Z129V 1Mb 128K x 8 ZEROPOWER SRAM PRELIMINARY DATA • INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS of DATA RETENTION in the