P3S12D30ETP Search Results
P3S12D30ETP Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
P3S12D40ETPContextual Info: 512Mb DDR Synchronous DRAM P3S12D30/40ETP DESCRIPTION P3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit, P3S12D40ETP is a 4-bank x 8,388,608-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output |
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512Mb P3S12D30/40ETP P3S12D30ETP 216-word P3S12D40ETP 608-word 16-bit, P3S12D30/40ETP 200MHz, |