SL9020 Search Results

Contextual Info: DATA CONTROLLER _ SL9020 PRELIMINARY FEATURES • Supports 80386,80386 SX P9 , or 80286-based AT designs. • Data In to Data Out time is 15 ns. • 24 mA output buffers. • Includes MD, SD & XD buffers. • 16 bit data path can be used as Low or High buffer.

block diagram of 80386dx microprocessor

Abstract: 80486 microprocessor pin out diagram sl90 SL9030 via flexset VIA SL9020 SL9020
Contextual Info: y/ a SL9020 Data Controller PRELIMINARY FEATURES • Supports 80286,80386SX, 80386DX, and 80486-based AT Designs. • Data In to Data Out: 15 ns. • 24 mA Output Buffers for SD Bus. • Includes MD, SD & XD Buffers. • 16 bit Data Path can be Used as Low or High Buffer.

T45 12H

Abstract: memory decoding 80386dx 16 bit sl90 LIM EMS 4.0 N804CS
Contextual Info: The FlexSet PC/AT 80386DX System & Memory Controller _ SL9352 PRELIMINARY FEATURES • 100% PC/AT Compatible. • Up to 20 MHz Performance. • ISA Bus Control Logic. • • • • • • Synchronous or Asynchronous System Control Operation.

386sx

Abstract: 386sx chipset A21-A23 sl9350 CHIPset for 80286 via flexset SL9151
Contextual Info: y/ a SL9250 80386SX Page Mode Memory Controller PRELIMINARY FEATURES • Supports 80386SX based AT Designs. • Up to 20 MHz Performance. • Enhanced Fast Page Mode DRAM Controller. • Supports 8 M byte of On-Board Memory. • Shadow RAM Feature. • Programmable Wait State Options.

T45 12H

Abstract: 80386dx pipeline ROY TODD 80386DX 16 BIT Code T6S intel 80386dx 80386DX NBS16 sl9030 SL903
Contextual Info: The FlexSet PC/AT 80386DX System & Memory Controller _ SL9352 PRELIMINARY FEATURES • 100% PC/AT Compatible. • Up to 20 MHz Performance. • ISA Bus Control Logic. • Synchronous or Asynchronous System Control Operation. • Programmable Command Delays.

80286 data bus MD

Abstract: MD10 MD11 MD14 SD14 SD15 SS2222
Contextual Info: D A T A CONTROLLER _ S L 90 20 PRELIMINARY FEATURES • Supports 80386,80386 SX P9 , or 80286-based AT designs. • Data In to Data Out time is 15 ns. • 24 mA output buffers. • Includes MD, SD & XD buffers. • 16 bit data path can be vised as Low or H igh buffer.

VIA SL9011

Contextual Info: The FlexSet PC/AT System Controller SL9011 PRELIMINARY FEATURES • AT System Control Logic. • Supports 80286,80386SX P9 , or 80386DX-based Designs. • Up to 25 MHz Performance. • Clock Switching and Reset Logic. • Programmable Wait States for 8 Bit AT Cycles.

386SX

Abstract: 5121M SL9010 D1384 intel 80386sx 80386SX 80386sx-based interleave SL9251 VIA SL9250
Contextual Info: The FlexSet PC/AT 80386SX Page Interleave M em ory Controller SL9251 PRELIMINARY FEATURES • Supports 80386SX based AT D esigns. • Up to 20 M Hz Performance. • Enhanced Fast Page M ode/Page Interleave. • Supports 8 M bytes of On-Board Memory. • Shadow RAM Feature

MSL9351

Abstract: DI512 sl9350 sl90 SL9351 SL9010
Contextual Info: The FlexSet PC/AT 80386DX Memory Controller _ SL9351 ADVANCED FEATURES • Supports 80386DX based AT Designs. • Up to 20 MHz Performance. • Enhanced Fast Page Mode/Page Interleave. • Supports 16 M bytes of On Board Memory. • Shadow RAM Feature

T44A

Abstract: 80286 microprocessor pin out diagram sl9030 t53a 80387SX weitek ti6a 80387DX 80386 microprocessor pin out diagram via flexset
Contextual Info: The FlexSet PC/AT System Controller SL9011 PRELIMINARY FEATURES • AT System Control Logic. • Supports 80286, 80386SX P9 , or 80386DX-based Designs. • Up to 25 MHz Performance. • Clock Switching and Reset Logic. • Programmable Wait States for 8 Bit AT Cycles.

T80-T

Abstract: toggle switch t80-t sl9030 LIM EMS 4.0 80387SX de-nor intel 80386sx 80386SX L73H N804CS
Contextual Info: The FlexSet PC/AT 80386SX System & M em ory Controller _ SL9252 PRELIMINARY FEATURES • 100% PC/AT Compatible. • Up to 20 MHz Performance. • ISA Bus Control Logic. • Synchronous or Asynchronous System Control Operation.

LIM EMS 4.0

Abstract: 80387
Contextual Info: The FlexSet PC/AT 80386SX System & Memory Controller _ SL9252 PRELIMINARY FEATURES • 100% PC/AT Compatible. • Up to 20 MHz Performance. • ISA Bus Control Logic. • • • • • • Synchronous or Asynchronous System Control Operation.

ta 8742 IC

Abstract: 80836DX 80286 mouse 386R sl90 SL9030 SL9010
Contextual Info: y/a SL9095 Power M anagement Unit PRELIMINARY FEATURES • Supports 80286, 80386SX, 80386DX, and 80486 Page Mode or Cache-based Laptop designs. • IBM PC/AT Compatible. • Software Programmable Power Management Unit. Provides Individual On/Off Control. • Compatible with all CPU Clock Rates.

VIA SL9030

Abstract: 80386SX core logic SL9025 313233 sl90 SL9030 PG52
Contextual Info: y/ a SL9025 Address Controller PRELIMINARY FEATURES • Supports 80286,80386SX P9 , 80386DX, and 80486-based AT Designs. • Address In to Address Out: 15 ns. • Up to 25 MHz Performance. • 24 mA Buffers. • Include SA & XA Buffers. • Includes XD to XA Transfer Latches.

DC000-DFFFF

Abstract: 80386dx pipeline architecture SL9351 DI512 386DX sl9010 80386DX 16 BIT 80386DX pipeline architecture for 80386DX A21-A23
Contextual Info: The FlexSet PC/AT 80386DX Memory Controller SL9351 ADVANCED FEATURES • Supports 80386DX based AT Designs. • Up to 20 MHz Performance. • Enhanced Fast Page Mode/Page Interleave. • Supports 16 M bytes of On Board Memory. • Shadow RAM Feature • 16K granularity

MSL9350

Abstract: 80386dx pipeline sl9350 via sl9350 via flexset
Contextual Info: SL9350 80386DX Page Mode Memory Controller PRELIMINARY FEATURES • Supports 80386DX based AT Designs. • Up to 25 MHz Performance. • Enhanced Fast Page Mode DRAM Controller. • Supports 16 M byte of on Board Memory. • Shadow RAM Feature. • Programmable Wait State Options.

weitek

Abstract: 80387DX sl9350 t46a 80X87 INTEL HT39A refresh logic sl90 t53a SL9030
Contextual Info: y/ à SL9011 System Controller PRELIMINARY FEATURES • AT System Control Logic. • Supports 80286,80386SX P9 , or 80386DX-based Designs. • Up to 25 MHz Performance. • Clock Switching and Reset Logic. • Programmable Wait States for 8 Bit AT Cycles.