SN74ALVC126 Search Results

A115-A

Abstract: SN74ALVC126 SN74ALVC126D SN74ALVC126DR SN74ALVC126NSR
Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111F – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)

SN74ALVC126

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: Contents Page ALVC Gates/Octals SN74ALVC00 SN74ALVC04 SN74ALVC08 SN74ALVC10 SN74ALVC14 SN74ALVC32 SN74ALVC74 SN74ALVC125 SN74ALVC126 SN74ALVC244 SN74ALVCH244 SN74ALVC245 SN74ALVCH245 SN74ALVCH373 SN74ALVCH374 2–2 Quadruple 2-Input Positive-NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

va126

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

SN74ALVC126

Abstract: SN74ALVC126D A115-A C101
Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 D EPIC  Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS S C E S 111 E - JULY 1997 - R EVISED FEB R U A R Y 1999 • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

A115-A

Abstract: C101 SN74ALVC126 SN74ALVC126D va126
Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com • • • • • SCES111I – JULY 1997 – REVISED JUNE 2004 Operates From 1.65-V to 3.6-V VCC Max tpd of 3.1 ns at 3.3-V VCC ±24-mA Output Drive at 3.3-V VCC Latch-Up Performance Exceeds 250 mA Per

VA126

Abstract: A115-A SN74ALVC126 SN74ALVC126D SN74ALVC126DR SN74ALVC126NSR
Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111F – JULY 1997 – REVISED MARCH 2002 D D D, DGV, NS, OR PW PACKAGE TOP VIEW Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)

A115-A

Abstract: C101 SN74ALVC126 SN74ALVC126D
Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

SN74ALVC126

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS S C E S 111C - JU LY 1997 - R EVISED FE BR U A R Y 1998 D, DGV, OR PW PACKAGE TOP VIEW E P IC (Enhanced-Performance Implanted CMOS) Submicron Process Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3ĆSTATE OUTPUTS SCES111G − JULY 1997 − REVISED AUGUST 2003 D D D D D D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

A115-A

Abstract: C101 SN74ALVC126 SN74ALVC126D VA126
Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES111J – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 3.1 ns at 3.3 V ±24-mA Output Drive at 3.3 V

msi 7267 MOTHERBOARD SERVICE MANUAL

Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Contextual Info: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

TTL 74-series IC LIST

Abstract: 74 Series Logic ICs TTL 74-series IC PO74G74 PO74G04 list cmos ics 49fct32805 49FCT3807 Potato Semiconductor 49FCT3805
Contextual Info: 04/18/07 Pin to Pin & Package to Package Compatible IC List Standard 1.65V -3.6 V TTL / CMOS Clock Buffer PotatoSemi PO49FCT3802A 1GHz 1 to 5 PO49FCT3803B 700MHz 1 to 7 PO49FCT3804 800MHz 2X1 to 4 PO49FCT3805B 800MHz 2X1 to 5 PO49FCT3806 750MHz 2X1 to 5 PO49FCT3807B

hct 4047 bt

Abstract: SN74ALS679 FCT Fast CMOS TTL Logic 74LS 4075 7804 inverter SN74368A DTL Logic 4069 CMOS hex inverter SN502 CD74AC374
Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

74HCT 4013

Abstract: CD4078 4093 BF SN74368A SN74ALS679 LXZ Series 4069 CMOS hex inverter 2a2 vacuum tube CD74AC374 cd408
Contextual Info: SN54HC240, SN74HC240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS128B – DECEMBER 1982 – REVISED MAY 1997 D D SN54HC240 . . . J OR W PACKAGE SN74HC240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers