SCEA004 Search Results

ALVCH16244

Abstract: ALVCH16835
Contextual Info: Timing Differences of 10-pF Versus 50-pF Loading SCEA004 November 1996 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information

Contextual Info: SN74LVCH162244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS545G – OCTOBER 1995 – REVISED JUNE 1999 D D D D D D D D D D D DL OR DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process

SCBA004C

Abstract: scaa035b
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS287 This data sheet is applicable to the CD54/74AC240, CD54ACT240, CD54AC241, and CD54/74ACT241. The CD74AC241 was not acquired from Harris Semiconductor. See SCHS244 for information on the CD74ACT240, CD74AC244, and CD74ACT244.

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339H – MARCH 1994 – REVISED OCTOBER 1998 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

Contextual Info: SN74ALB16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS647C – AUGUST 1995 – REVISED JULY 1997 D D D D D D D DGG OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus  Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for 3.3-V

Contextual Info: SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

pinout diagram of 4049

Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54/74HC4049, CD54/74HC4050 Data sheet acquired from Harris Semiconductor SCHS205B High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised May 2000 Features

Contextual Info: SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398C – APRIL 1998 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C

abt244a

Abstract: Texas Instruments Power Supply
Contextual Info: SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS184D – JANUARY 1991 – REVISED JANUARY 1997 D D D D SN54ABT241 . . . J OR W PACKAGE SN74ABT241A . . . DB, DW, N, OR PW PACKAGE TOP VIEW 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 20

Contextual Info: SN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDAS142C – JULY 1987 – REVISED AUGUST 1995 • • SN54ALS244C, SN54AS244A . . . J PACKAGE SN74ALS244C, SN74AS244A . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer

Contextual Info: SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDAS025C – APRIL 1982 – REVISED JANUARY 1995 • • • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Data Flow-Through Pinout All Inputs on

Contextual Info: SN54LVTH125, SN74LVTH125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SCBS703F – AUGUST 1997 – REVISED JUNE 2000 D D D D D D D SN54LVTH125 . . . J PACKAGE SN74LVTH125 . . . D, DB, DGV, OR PW PACKAGE TOP VIEW 1OE 1A 1Y 2OE 2A 2Y GND 1 14 2 13

Contextual Info: SN54LV541A, SN74LV541A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS410D – APRIL 1998 – REVISED MAY 2000 D D D D D D SN54LV541A . . . J OR W PACKAGE SN74LV541A . . . DB, DGV, DW, NS, OR PW PACKAGE TOP VIEW OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19

Contextual Info: SN54ALVTH16827, SN74ALVTH16827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES076E – JULY 1996 – REVISED DECEMBER 1998 D D D D D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology ABT Widebus  Design for 2.5-V and 3.3-V Operation and Low Static

SCHS046A

Abstract: CD4050BE ic 16 pin diagram CD4049 pin configuration not gate CD4050B dtl ttl logic GUIDE
Contextual Info: CD4049UB, CD4050B August 1998 - Revised May 1999 Data sheet acquired from Harris Semiconductor SCHS046A [ /Title CD40 49UB, CD405 0B /Subject (CMO S Hex Buffer/ Converters) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS CMOS Hex Buffer/Converters

Contextual Info: SN54ABT827, SN74ABT827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS159D – JANUARY 1991 – REVISED MAY 1997 D D D D D D D State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout

Contextual Info: SN54LVC540A, SN74LVC540A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS297H – JANUARY 1993 – REVISED JUNE 1998 D D D D D description The SN54LVC540A octal buffer/driver is designed for 2.7-V to 3.6-V VCC operation and the SN74LVC540A octal buffer/driver is designed for

Contextual Info: SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 D D D D D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology ABT Widebus  Design for 2.5-V and 3.3-V Operation and Low Static

Contextual Info: SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398C – APRIL 1998 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS516B – JUNE 1995 – REVISED MAY 1996 D SN54ACT241 . . . J OR W PACKAGE SN74ACT241 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54AHC126, SN74AHC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS257K – DECEMBER 1995 – REVISED FEBRUARY 2002 D D SN54AHC126 . . . J OR W PACKAGE SN74AHC126 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per

SN74AHCT244PWR

Contextual Info: SN54AHCT244, SN74AHCT244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS228K – OCTOBER 1995 – REVISED MAY 2002 SN54AHCT244 . . . J OR W PACKAGE SN74AHCT244 . . . DB, DGV, DW, N, NS, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per

Contextual Info: SN54LV07A, SN74LV07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCES337E – MAY 2000 – REVISED NOVEMBER 2001 D D D D D SN54LV07A . . . J OR W PACKAGE SN74LV07A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: SN64BCT244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS027A – FEBRUARY 1989 – REVISED JANUARY 1994 • • • • • DW OR N PACKAGE TOP VIEW State-of-the-Art BiCMOS Design Significantly Reduces ICCZ 3-State Outputs Drive Bus Lines or Buffer-Memory Address Registers