T48LC Search Results

EE-19

Abstract: 8M16 MT48LC16M8A2 MT48LC16M8A2TG-8E MT48LC32M4A2 MT48LC8M16A2 ck cl v2a
Contextual Info: SYNCHRONOUS DRAM M T48LC 32M 4A 2- 8 Meg x 4 x 4 banks M T48LC 16M 8A 2- 4 Meg x 8 x 4 banks T48LC8M16A2 -2 Meg x 16 x 4 banks For the latest data sheet, please re fe r to the M icron Web site: w w w ,m icron .com lm ti/m sp lhim lfd a tsshe ei.h im i FEATURES

Contextual Info: M il“ C a a iS J I L IL z 64Mb: x4, x8, x16 SDRAM M T48LC16M 4A2 -4 Meg x 4 x 4 banks M T48LC 8M 8A 2- 2 Meg x 8 x 4 banks M T48LC4M 16A2 -1 Meg x 16 x 4 banks SYNCHRONOUS DRAM For the latest data sheet, please refer to the Micron Web site: www,micron.com/mti/msp/html/datasheet.html

MT48LC4M4R1

Abstract: marking a5 4r
Contextual Info: ADVANCE l^iicnoN M T48LC 4M 4R 1 4 M EG X 4 S D R A M X 4 SDRAM 3.3 VOLT, PULSED RAS, DUAL BANK, SELF REFRESH FEATURES PIN ASSIGNMENT Top View • Fully synchronous; all signals (excluding dock enable) registered to positive edge of system clock • Dual 2 Meg x 4s, separate, internal banks controlled by

Contextual Info: PRELIMINARY 128Mb: x4, x8, x16 SDRAM MICRON' I TECHNOLOGY, INC. M T48LC32M 4A2 - 8 Meg x 4 x 4 banks M T48LC16M 8A2 - 4 Meg x 8 x 4 banks M T48LC8M 16A2 - 2 Meg x 16 x 4 banks SYNCHRONOUS DRAM For the latest full-length data sheet, please refer to the Micron

Contextual Info: PRELIMINARY M I C R O I N 16 M E G : x 4 ’ x 8 SDRAM TECHNOLOGY, INC. C V K i r U P b Y N l / H n U A M N A I U I C U M T 4 8 L C 4 M 4 A 1 S 4 M e g x 4 M T48LC 2M 8A 1 S ( 2 M e g x 8 ) b DRAM FEATURES PIN ASSIGNMENT (TOP VIEW) • Fully synchronous; all signals registered on positive

Contextual Info: 64 M E G :X 4e X nnX A M MICRON I TECHNOLOGY, INC. Q ^ ^ jy j T48LC16M4A1 /A2 -4 Meg x 4 x 4 banks M T48LC8M 8A1/A2 - 2 Meg x 8 x 4 banks M T48LC4M 16A1/A2 -1 Meg x 16 x 4 banks SYNCHRONOUS DRAM For the latest data sheet revisions, please refer to the Micron

Contextual Info: ADVANCE M T48LC 4M 4R 1 S 4 MEG X 4 SDRAM l ^ lld R O N 4 MEG SYNCHRONOUS DRAM 4 SDRAM X Pulsed RAS, Dual Bank, BURST Mode, 3.3V, SELF REFRESH PIN ASSIGNMENT (Top View) • Fully synchronous; all signals (excluding clock enable) registered to positive edge of system clock

9845M

Contextual Info: 16M lnbX A M MICRON I TECHNOLOGY, INC. Q SYNCHRONOUS DRAM M T48LC 1M 16A1 V dd DQO DQ1 VssQ DQ2 DQ3 V ddQ DQ4 DQ5 VssQ DQ6 DQ7 V ddQ DQM L W E# C AS# RAS# C S# BA A10 AO A1 A2 A3 V dd 1M16 TG • Tim ing Cycle Time 8ns, *AC = 6ns @ CL = 3 10ns, *AC = 9ns @ CL = 2

MT48LC2M8S1

Abstract: 1993 synchronous dram jedec A221D 1993 SDRAM
Contextual Info: ADVANCE M T48LC2M 8S1 2 MEG X 8 SDRAM p ilC R O N 3.3 VOLT, PULSED RAS, DUAL BANK, SELF REFRESH FEATURES PIN ASSIGNMENT Top View • Fully synchronous; all signals (excluding clock enable) registered to positive edge of system clock • Dual 1 Meg x 8s, separate, internal banks controlled by A ll

tl 2345 ml

Contextual Info: ADVANCE 64Mb: x32 SDRAM M T48LC2M 32B2 - 512K x 32 x 4 banks SYNCHRONOUS DRAM For the latest full-length data sheet, please refer to the Micron Web site: www. micron, com/mti/rnsp/htrnl/ datasheet him! FEATURES PIN ASSIGNMENT Top View • PC100 functionality

Contextual Info: PRELIMINARY MICRON I 4’ 8 M E Gx64 SDRAM SODIMMs TECHNOLOGY, INC. SMALL-OUTLINE -s = WT | j Q II I t U n n i V I For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html II I t I I | j I I I I

Contextual Info: 16Mb: x16 SDRAM M IC R O N I TECHNOLOGY, INC. M T 4 8 L C 1 M 1 6 A 1 S - 5 1 2 K X 16 X 2 b a n k s SYNCHRONOUS DRAM F or the la te st full-length data sheet, please re fe r to the M icron Web site : www. m icron, com /m ti/m sp/htm l/datasheet. htm ! FEATURES

1994 sdram

Abstract: 48LC2M
Contextual Info: ADVANCE l^ ic n o N T48LC2M8K3 S 2 MEG x 8 SDRAM 2 MEG x 8 SDRAM H D A M IJ n * * I V I Level RAS, Single Bank, BURST Mode, 3.3V, SELF REFRESH PIN ASSIGNMENT Top View • Fully synchronous; all signals registered to positive edge of system clock • JEDEC-standard 3.3V power supply

sdram schematic diagram

Abstract: MT48LC1M16A1S D4564163 AN218 EP7312 a2523 MT48LC4M16A2
Contextual Info: AN218 Application Note INTERFACING THE EP7312 WITH SDRAM 1. INTRODUCTION The focus of this note is to aid product developers in successfully creating an EP7312 design that utilizes SDRAM. It does not cover the software configuration or internal operation of the

Contextual Info: ADVANCE MICRON 32 M EGx64 I SDRAM DIMM MT16LSDT3264A SYNCHRONOUS DRAM MODULE For the latest full-length data sheet, please refer to the Micron Web site: www.micron.com /m ti/m sp/htm l/ datasheet.html FEATURES PIN ASSIGNMENT Front View • PCIOO-compliant; includes CON CURREN T AUTO

DQ131

Abstract: MT48LC16M16A2TG8E
Contextual Info: ADVANCE M IC R O N * I 2 56 M b : xV TCCHW LOOY.INC. SYNCHRONOUS DRAM nV ,1,5 SD R A M T48LC64M4A2 - 16 Meg x 4 x 4 banks T48LC32M8A2 - 8 Meg x 8 x 4 banks T48LC16M16A2 - 4 Meg x 16 x 4 banks For the latest data sh ee t revisions, p le a s e refer to the Micron

marking code 17W

Abstract: ZM marking
Contextual Info: OBSOLETE 2, 4 MEG X 72 SDRAM DIMMs MICRON I TECHNOLOGY, INC. MT9LSDT272A, MT18LSDT472A SYNCHRONOUS DRAM MODULE For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Front View

Contextual Info: 4’8 M E Gx64 MICRON I SDRAM SODIMMs TECHNOLOGY, INC. SM ALL-OUTLINE li il I l A ^ l l f l RA MT4LSDT464H, MT8LSDT864H I II For the latest data sheet revisions, please refer to the Micron Web site: www.m icron.com/m ti/msp/htm l/datasheet.htm l IV I FEATURES

Contextual Info: 4, 8 MEG X 72 SDRAM DIMMs MT5LSDT472A, MT5LSDT872A SYNCHRONOUS DRAM MODULE For the latest data sheet, please refer to the Micron Web site: www.m icron.com /m ti/m sp/htm l/datasheet.htm i FEATURES PIN ASSIGNMENT Front View • PC66-*, PC100- and PC133-compliant

MT48LC2M8S1

Contextual Info: MICRON S E M I C O N D U C T O R INC b3E D • b 1 1 3.54T Ü G G 7 7 1 0 217 « M R N ADVANCE M I i m n N sEM icoNoucroti inc. M T4 8 L C 2 M 8 S 1 2 M EG X 8 SD RA M X 8 SDRAM 3.3 VOLT, PULSED RAS, DUAL BANK, SELF REFRESH FEATURES • Fully synchronous; all signals excluding clock enable

Contextual Info: ADVANCE 2, 4 MEG X 72 SDRAM DIMMs MICRON I TECHNOLOGY, INC. SYNCHRONOUS DRAM MODULE MT9LSD T 272A MT18LSD(T)472A FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • Utilizes 83 and 100 MHz SDRAM components

Contextual Info: ADVANCE MICRON I 1 , 2 MEG X 32 SDRAM DIMM TECHNOLOGY, INC. SYNCHRONOUS ¡¡£fg * I JU For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html IWI a \ IWI f J I J I I I I V I V / I / w FEATURES

"LCK"

Contextual Info: PRELIMINARY 16 MEG: x16 SDRAM MICRON I TKtHOLMTT, INC. SYNCHRONOUS DRAM T48LC1M16A1 S - 51 2K x 16 x 2 banks FEATURES • PCIOO-compliant functionality • Fully synchronous; all signals registered on positive edge of system clock • In tern al p ip elin ed operation; colum n ad d ress can be

Contextual Info: ADVANCE 16 MEG x 72 PC133 REGISTERED SDRAM DIMM MICRON I TECHNOLOGY, INC. SYNCHRONOUS DRAM MODULE M T18LSD T1672 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Front View