T7229 Search Results

cem 5161

Abstract: T7229 T7229-PC T-7229
Contextual Info: Preliminary T7229 Primary Access Framer Features • Multiple line format capability a AMI and HDB3 CEPT □ Bipolar and B8ZS ■ Remote frame/multiframe alarm activation and detection ■ Multiple DS1 TDM frame formats a Independent formats - D4, SLC Carrier,

229GB

Abstract: 257AU
Contextual Info: 257AU Receive Synchronizer Features • Selectable DS1 1.544 M b/s or CEPT (2.048 M b/s) form ats Single 5 V supply TTL-com patlbie inputs and outputs ■ 4- o r 16-state RSM signal extraction ■ Internal m aintenance circuits Description The 257AU Receive Synchronizer (RS) is part of an LSI digital fa cility interface chip set that also

IR receiver TK 19 544

Abstract: IR receiver TK 19 527 229GB T7229 fault codes for RBS sr62
Contextual Info: 229GB Primary Access Framer Features • Bipolar and B8ZS line format capability ■ Multiple DS1 TDM frame formats D Independent formats - D4 channel bank D4 , SLC 96 Carrier (SL), extended superframe (ESF), and digital data system T1 digital multiplexer (DDS)

72284

Abstract: IR 536
Contextual Info: VARIABLE WIDTH CMOS SUPERSYNC FIFO 32,768 x 18 or 65,536 x 9 65,536x18 or 131,072x9 PRELIMINARY IDT72284 T72294 Integrated Device Technology. Inc. FEATURES: Independent Read and W rita clocks permit reading and writing simultaneously} VSSi * Choose among the following memory organizations:

72284

Contextual Info: VARIABLE WIDTH CMOS SUPERSYNC FIFO 3 2,768x18 or 65,536x9 65,536x18 or 131,072x9 PRELIMINARY IDT72284 T72294 Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72284 32,768 x 18 or 65,536 x 9 T72294

72284

Contextual Info: V A R IA B L E W ID T H S U P E R S Y N C FIF O 3 2 ,7 6 8 x 18 o r 6 5 ,5 3 6 x 9 6 5 ,5 3 6 x 18 o r 13 1 ,0 7 2 x 9 FEATURES: • Choose among the following memory organizations: IDT72284 32,768 x 18 or 65,536 x 9 T72294 65,536 x 18 or 131,072 x 9

T7230

Contextual Info: Preliminary Data Sheet March 1992 / s AT&T - Microelectronics T7230 Primary Access Framer/Controller PAC Features • Framing formats: — DS1 (1.544 M bits/s): ESF; D4; SZ.C -96; DDS; DDS with FDL access — Programmable independent transm it and receive framing mode when using the ESF

Contextual Info: CMOS SUPERSYNC FIFO 65,536 x 9 131,072x9 PRELIMINARY IDT72281 T72291 Integrated De'v i e Technoi>gy, l i e . FEATURES: • Choose among the following memory organizations: IDT72281 65,536 x 9 T72291 131,072x9 • Pin-compatible with the IDT72261 LA/72271 LA SuperSync FIFOs

72284

Contextual Info: VARIABLE WIDTH CMOS SUPERSYNC FIFO 32,768 x 18 or 65,536 x 9 65,536 x 18 or 131,072 x 9 FEATURES: • Choose among the following memory organizations: IDT72284 32,768 x 18 or 65,536 x 9 T72294 65,536 x 18 or 131,072 x 9 • Pin-compatible with the IDT72261/72271, IDT72255/72265

Contextual Info: 257AL Transm it Form atter Features • 2-, 4-, 16-state signaling or inhibit signaling ■ Variable F-bit and parity-bit delays ■ Selectable DS1 1.544 Mb/s or CEPT (2.048 Mb/s) formats ■ TTL-compatible Description The 257AL Transmit Formatter integrated circuit converts 14 bits of parallel data (8 traffic bits, 5

229FB

Abstract: 229GB T7229 GPL11 GPL01
Contextual Info: 229FB Maintenance Buffer Features • 8 -bit interface bus ■ M icroprocessor access to co n tro l/re p o rt streams ■ Ten general-purpose latched outputs ■ Preprocessing counters on fa cility error conditions updated by the framer ■ Built-in operational testing capability

GSIG

Abstract: T7229 E12E13 257al 229GB
Contextual Info: 257AL Transmit Form atter Features • 2-, 4-, 16-state signaling or inhibit signaling Variable F-bit and parity-bit delays ■ Selectable DS1 1.544 Mb/s or CEPT (2.048 Mb/s) formats TTL-compatible Description The 257AL Transmit Formatter integrated circuit converts 14 bits of parallel data (8 traffic bits, 5